DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 18

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

3 0 Buffer Management
All RRA registers are concatenated with the URRA register
for generating the full 32-bit address
The resource descriptors that the system writes to the RRA
consists
RXrsrc buff ptr1
RXrsrc buff wc1 The fields must be contiguous (they can-
not straddle the end points) and are written in the order
shown in Figure 3-8 The ‘‘0’’ and ‘‘1’’ in the descriptors
denote the least and most significant portions for the Buffer
Pointer and Word Count The first two fields supply the 32-
bit starting location of the Receive Buffer Area (RBA) and
the second two define the number of 16-bit words that the
RBA occupies
Note that two restrictions apply to the Buffer Pointer and
Word Count First in 32-bit mode since the SONIC always
writes long words an even count must be written to
RXrsrc buff wc0 Second the Buffer Pointer must either
be pointing to a word boundary in 16-bit mode (A0
long word boundary in 32-bit mode (A0 A1
that the descriptors must be properly aligned in the RRA as
discussed in Section 3 3
After configuring the RRA the RRA Read command (setting
RRRA bit in the Command register) may be given This
command causes the SONIC to read the RRA descriptor in
a single block operation and load the following registers
(see Section 4 2 for register mnemonics)
CRBA0 register
CRBA1 register
RBWC0 register
RBWC1 register
When the command has completed the RRRA bit in the
Command register is reset to ‘‘0’’ Generally this command
is only issued during initialization At all other times the RRA
is automatically read as the SONIC finishes using an RBA
3 4 4 3 Initializing The RDA
To accept multiple packets from the network the receive
packet descriptors must be linked together via the
RXpkt link fields Each link field must be written with a 15-bit
(A15 –A1) pointer to locate the beginning of the next de-
scriptor in the list The LSB of the RXpkt link field is the End
of List (EOL) bit and is used to indicate the end of the de-
scriptor list EOL
the first or middle descriptors The RXpkt in use field indi-
cates whether the descriptor is owned by the SONIC The
system writes a non-zero value to this field when the de-
scriptor is available and the SONIC writes all ‘‘0’s’’ when it
finishes using the descriptor At startup the Current Receive
Descriptor Address (CRDA) register must be loaded with the
address of the first RXpkt status field in order for
of
FIGURE 3-8 RRA Initialization
four
e
1 for the last descriptor and EOL
RXrsrc buff ptr0
RXrsrc buff ptr1
RXrsrc buff wc0
RXrsrc buff wc1
(3)
fields
RXrsrc buff wc0
(1)
RXrsrc buff ptr0
(Continued)
e
0 0) Note also
TL F 10492–15
and
e
e
0) or a
0 for
(2)
(4)
18
the SONIC to begin receive processing at the first descrip-
tor An example of two descriptors linked together is shown
in Figure 3-9 The fields initialized by the system are dis-
played in bold type The other fields are written by the
SONIC after a packet is accepted The RXpkt in use field
is first written by the system and then by the SONIC Note
that the descriptors must be aligned properly as discussed
in Section 3 3 Also note that the URDA register is concate-
nated with the CRDA register to generate the full 32-bit ad-
dress
3 4 4 4 Initializing the Lower Boundary of the RBA
A ‘‘false bottom’’ is set in the RBA by loading the End Of
Buffer Count (EOBC) register with a value equal to the maxi-
mum size packet in words (16 bits) that may be received
This creates a lower boundary in the RBA Whenever the
Remaining Buffer Word Count (RBWC0 1) registers decre-
ment below the EOBC register the SONIC buffers the next
packet into another RBA This also guarantees that a pack-
et is always contiguously buffered into a single Receive
Buffer Area (RBA) The SONIC does not buffer a packet into
multiple RBAs Note that in 32-bit mode the SONIC holds
the LSB always low so that it properly compares with the
RBWC0 1 registers
After a hardware reset the EOBC reset the EOBC register
is automatically initialized to 2F8h (760 words or 1520
bytes) For 32-bit applications this is the suggested value for
EOBC EOBC defaults to 760 words (1520 bytes) instead of
759 words (1518 bytes) because 1518 is not a double word
(32-bit) boundary (see Section 3 4 2 1) If the SONIC is used
in 16-bit mode then EOBC should be set to 759 words
(1518 bytes) because 1518 is a word (16-bit) boundary
Sometimes it may be desired to buffer a single packet per
RBA When doing this it is important to set EOBC and the
buffer size correctly The suggested practice is to set EOBC
to a value that is at least 4 bytes in 32-bit mode or 2 bytes
in 16-bit mode less than the buffer size An example of this
for 32-bit mode is to set EOBC to 760 words (1520 bytes)
FIGURE 3-9 RDA Initialization Example
TL F 10492 – 16