DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 81

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

Number
T9
T11a
T11c
T12a
T12c
T13a
T13b
T14
T15a
T18
T19
T20
T22
T30
T30a
T31
T31a
T36
T37a
T39
7 0 AC and DC Specifications
Note 1 For successive write operations MRW remains low
Note 2 Meeting the setup time for DSACK0 1 or STERM guarantees that the SONIC will terminate the memory cycle 1
sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK0 1 or STERM are sampled properly in a low state If the SONIC samples
DSACK0 1 or STERM low during the T1 or first T2 state respectively the SONIC will finish the current access in a total of two bus clocks instead of three (assuming
that programmable wait states are set to 0) DSACK0 1 are asynchronously sampled and STERM is synchronously sampled
Note 3 DS will only be asserted if the bus cycle has at least one wait state inserted
Note 4 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing)
BSCK to Address Valid
BSCK to AS Low
BSCK to ECS Low
BSCK to AS High
BSCK to ECS High
BSCK to DS Low
BSCK to DS High
AS Low Width
AS High Width
Write Data Strobe Low Width (Note 3)
Address Hold Time from AS
Data Hold Time from AS
Address Valid to AS
DSACK0 1 Setup to BSCK (Note 2)
STERM Setup to BSCK (Note 2)
DSACK0 1 Hold from BSCK
STERM Hold from BSCK
BSCK to Memory Write Data Valid (Note 4)
BSCK to MRW (Write) Valid (Note 1)
Write Data Valid to Data Strobe Low
Parameter
(Continued)
81
Min
18
20
44
45
40
34
3
9
5
5
9
8
3
20 MHz
Max
26
17
19
17
19
16
16
50
26
Min
34
35
30
14
16
21
3
6
8
7
4
4
3
25 MHz
Max
24
15
17
15
17
14
14
48
24
bus clocks after DSACK0 1 were
Min
24
25
20
10
12
3
2
3
3
7
6
3
7
33 MHz
Max
22
13
15
13
15
12
12
46
22
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns