DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 54

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

5 0 Bus Interface
5 4 2 Block Transfers
The SONIC performs block operations during all bus ac-
tions thereby providing efficient transfers to memory The
block cycle consists of three parts The first part is the bus
acquisition phase as discussed above in which the SONIC
gains access to the bus Once it has access of the bus the
SONIC enters the second phase by transferring data
to from its internal FIFOs or registers from to memory The
SONIC transfers data from its FIFOs in either EXACT
BLOCK mode or EMPTY FILL
EXACT BLOCK mode In this mode the number of words
(or long words) transferred during a block transfer is deter-
mined by either the Transmit or Receive FIFO thresholds
programmed in the Data Configuration Register
EMPTY FILL mode In this mode the DMA completely fills
the Transmit FIFO during transmission or completely emp-
ties the Receive FIFO during reception This allows for
greater bus latency
When the SONIC accesses the Descriptor Areas (i e RRA
RDA CDA and TDA) it transfers data between its registers
and memory All fields which need to be used are accessed
in one block operation Thus the SONIC performs 4 ac-
cesses in the RRA (see Section 3 4 4 2) 7 accesses in the
RDA (see Section 3 4 6 1) 2 3 or 6 accesses in the TDA
(see Section 3 5 4) and 4 accesses in the CDA
5 4 3 Bus Status
The SONIC presents three bits of status information on pins
S2 –S0 which indicate the type of bus operation the SONIC
is currently performing (Table 5-2) Bus status is valid at the
falling edge of AS or the rising edge of ADS
(Continued)
FIGURE 5-6 Bus Request Timing BMODE
54
S2
1
1
0
0
0
1
1
0
S1
1
0
0
1
1
1
0
0
S0
1
1
1
1
0
0
0
0
e
TABLE 5-2 Bus Status
1
The bus is idle The SONIC is not
performing any transfers on the bus
The Transmit Descriptor Area (TDA) is
currently being accessed
The Transmit Buffer Area (TBA) is
currently being read
The Receive Buffer Area (RBA) is
currently being written to Only data is
being written though not a Source or
Destination address
The Receive Buffer Area (RBA) is
currently being written to Only the
Source or Destination address is being
written though
The Receive Resource Area (RRA) is
currently being read
The Receive Descriptor Area (RDA) is
currently being accessed
The CAM Descriptor Area (CDA) is
currently being accessed
Status
TL F 10492 – 28