28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 85

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

behaves as a PCI slave device while data is being read or written by the host. MUSYCC responds to all access
cycles where the upper 12 bits of a PCI address match the upper 12 bits of either the EBUS Base Address register
(Function 1) or the MUSYCC Base Address register (Function 0).
For MUSYCC’s Function 1, a 1 MB memory space is assigned to the EBUS Base Address register which is written
into Function 1 PCI configuration space
can then be allocated memory addresses within this 1 MB memory range. If MUSYCC claims a PCI access cycle
for Function 1, MUSYCC initiates EBUS arbitration and ultimately accesses data from a device connected to the
EBUS.
For MUSYCC’s Function 0, a 1 MB memory space is assigned to the MUSYCC Base Address register which is
written into Function 0 PCI configuration space
assigned to Function 0, a register map is used to access individual device resident registers. The register map
provides the byte offset from the Base Address register where registers reside. The register map layout is listed in
Table
The 1 MB memory ranges assigned to MUSYCC functions will not restrict MUSYCC’s PCI interface from
attempting to access these ranges. The host must be cognizant that MUSYCC cannot respond to an access cycle
which MUSYCC itself initiates as the bus master.
Table 5-1.
28478-DSH-002-E
Group Base Pointer
Dual Address Cycle Base Pointer
Service Request Descriptor
Interrupt Status Descriptor
Transmit Time Slot Map
Transmit Subchannel Map
Transmit Channel Configuration Table
Receive Time Slot Map
Receive Subchannel Map
Receive Channel Configuration Table
Global Configuration Descriptor
Interrupt Queue Descriptor
Group Configuration Descriptor
Memory Protection Descriptor
Message Length Descriptor
Port Configuration Descriptor
5-1.
Register Map
MUSYCC Register Map (1 of 2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
Preliminary Information / Mindspeed Proprietary and Confidential
(2)
(2)
0000h
0008h
0200h
0280h
0380h
0400h
0480h
0580h
060Ch
0610h
0614h
0618h
Mindspeed Technologies
0
(Table 2-14, Register 4, Address
0D80h
0800h
0808h
0A00h
0A80h
0B80h
0C00h
0C80h
0E0Ch
0E10h
0E14h
0E18h
(Table 2-7, Register 4, Address
1
(Byte Offset from Base Address Register)
1000h
1008h
1200h
1280h
1380h
1400h
1480h
1580h
160Ch
1610h
1614h
1618h
2
1A00h
1A80h
1B80h
1C00h
1C80h
1D80h
1E0Ch
1800h
1808h
1E10h
1E14h
1E18h
®
3
00004h
00600h
00604h
Group
000Ch
10h). Devices connected to the EBUS
2000h
2580h
260Ch
2008h
2200h
2280h
2380h
2400h
2480h
2610h
2614h
2618h
4
10h). Once a base address is
2800h
2808h
2A00h
2A80h
2B80h
2C00h
2C80h
2D80h
2E0Ch
2E14h
2E18h
2E10h
Memory Organization
5
3000h
3008h
3200h
3280h
3380h
3400h
3480h
3580h
360Ch
3610h
3614h
3618h
6
3D80h
3800h
3808h
3A00h
3A80h
3B80h
3C00h
3C80h
3E0Ch
3E10h
3E14h
3E18h
7
72