28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 84

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Figure 5-1.
5.1.1
During MUSYCC’s PCI initialization, the system controller allocates a dedicated 1 MB memory range to each of
MUSYCC’s PCI functions. The memory range allocated to MUSYCC must not map to any other physical or shared
memory. Instead, the system configuration manager allocates a logical memory address range, and notifies the
system or bus controllers that any access to these ranges must result in a PCI access cycle. MUSYCC is assigned
these address ranges for each function through the PCI configuration cycle. Once configured, MUSYCC becomes
a functional PCI device on the bus.
As the host accesses MUSYCC’s allocated address ranges, it initiates the access cycles on the PCI bus. It is up to
individual MUSYCC devices on the bus to claim the access cycle. As its address ranges are accessed, MUSYCC
28478-DSH-002-E
8478_021
Tx Message Pointer – Ch .....
Rx Message Pointer – Ch 31
Tx Message Pointer – Ch 00
Tx Message Pointer – Ch 31
Rx Message Pointer – Ch 00
Rx Message Pointer – Ch ....
Shared Memory Model Per Channel Group
Channel Group Descriptor
Rx Head Pointer – Ch 00
Rx Head Pointer – Ch 31
Tx Head Pointer – Ch 00
Tx Head Pointer – Ch.....
Tx Head Pointer – Ch 31
Rx Head Pointer – Ch ....
Rx Channel Config Table
Tx Channel Config Table
Global Configuration
Rx Subchannel Map
Group Configuration
Tx Subchannel Map
Group Base Pointer
Memory Protection
Rx Time Slot Map
Port Configuration
Register Map Access and Shared Memory Access
Tx Time Slot Map
Message Length
Interrupt Queue
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
* See Table 5-19 for structure of Message Descriptor.
Next Message Pointer
Next Message Pointer
Next Message Pointer
Next Message Pointer
Next Message Pointer
Next Message Pointer
Data Buffer Pointer
Data Buffer Pointer
Data Buffer Pointer
Data Buffer Pointer
Data Buffer Pointer
Data Buffer Pointer
Buffer Descriptor
Buffer Descriptor
Buffer Descriptor
Buffer Descriptor
Buffer Descriptor
Buffer Descriptor
®
Transmit Message List
Receive Message List
Memory Organization
Data Buffer
Data Buffer
Data Buffer
Data Buffer
Data Buffer
Data Buffer
71