28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 158

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

6.4.8.4.4
Out-of-frame or loss-of-frame indicates that the entire serial data stream is invalid and data cannot be recovered
from such a signal. In this case, out-of-frame of the incoming signal occurred while in the midst of receiving an
HDLC message and copying the data to shared memory.
Reason:
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Effects:
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Channel Level Recovery Actions:
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6.4.8.4.5
In the case of an FCS error, the frame check sequence (or CRC) calculated for the received HDLC message by
MUSYCC does not match the FCS sent within the HDLC message.
Reason:
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Effects:
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Channel Level Recovery Actions:
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28478-DSH-002-E
MUSYCC writes the T1/E1 signal failure is detected by the physical interface providing the serial data, clock
frequency, and synchronization to the serial interface on MUSYCC.
MUSYCC writes the Interrupt Descriptor in Interrupt Queue with ERROR = OOF, DIR = 0 (if MSKOOF = 0 in
Group Configuration Descriptor).
If bit field OOFABT = 0, BLP, and DMAC continue as if no errors occurred and transfer received data into
shared memory buffers normally.
If bit field OOFABT = 1 and is currently receiving an HDLC message, the received data in the internal FIFO
buffer is discarded and lost to the host. DMAC accesses the Next Message Pointer from the current Message
Descriptor. MUSYCC returns ownership of the current Message Descriptor by writing the Receive Buffer
Status Descriptor with ONR = HOST, ERROR = OOF (if INHRBSD = 0 in Receive Channel Configuration
Descriptor).
Regardless, the BLP continues scanning for opening flag.
Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared
memory.
Receive channel recovers automatically.
None required.
Bit errors during transmission.
The Interrupt Descriptor in Interrupt Queue with ERROR = FCS, DIR = 0 (if MSKMSG = 0 in Channel
Configuration Descriptor).
The entire HDLC message already copied to shared memory buffers.
DMAC accesses the Next Message Pointer from the current Message Descriptor.
Returns ownership of the current Message Descriptor to the host by writing the Receive Buffer Status
Descriptor with ONR = HOST, ERROR = FCS (if INHRBSD = 0 in Channel Configuration Descriptor).
The BLP scans for the opening flag of the next HDLC message.
Simultaneously, DMAC checks for Message Descriptor ownership before transferring received data to shared
memory.
None required.
Out of Frame (OOF)
Frame Check Sequence (FCS) Error
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