28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 156

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Channel Level Recovery Actions:
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6.4.8.4
Receive errors are service-affecting and require a corrective action by the host to resume normal bit-level
processing.
6.4.8.4.1
In the case of overflow due to host ownership of the buffer while receiving an HDLC message, MUSYCC attempts
to access the next Message Descriptor to store a message or part of a message, and finds that ownership of the
descriptor has not been granted by the host.
This error results when currently receiving an HDLC message, and no additional descriptors are available in a
timely manner.
Once a descriptor is granted, however, MUSYCC assumes ownership of the message buffer and continues writing
data until the end of buffer is reached. If the host reclaims the buffer without MUSYCC granting ownership back to
the host, a host error occurs and the effects are indeterminate.
Reason:
•
Effects:
•
•
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•
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Channel Level Recovery Actions:
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6.4.8.4.2
In the case of overflow due to internal FIFO buffer overrun, the internal FIFO buffer has not been completely copied
to shared memory before more data bits arrive needing to be stored in the FIFO buffer. MUSYCC has access to a
message buffer space in shared memory in this case.
Reasons:
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Effects:
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28478-DSH-002-E
Transmit channel reactivation is required.
Degradation of host subsystem or application software performance.
Interrupt Descriptor in Interrupt Queue with ERROR = ONR, DIR = 0
(if MSKBUFF = 0 in Receive Channel Configuration Descriptor).
The received data in the internal FIFO buffer is discarded and lost to the host.
The remainder of the HDLC message currently being received is discarded.
The Receive Buffer Status Descriptor cannot be written.
The channel is deactivated.
Provide sufficient amount of shared memory to store received data using the lists of Message Descriptors with
ownership granted to MUSYCC.
Reactivate channel.
Degradation of host sub system performance.
Congestion of the PCI bus.
The Interrupt Descriptor in Interrupt Queue with ERROR = BUFF, DIR = 0 (if MSKBUFF = 0 in Receive
Channel Configuration Descriptor).
Receive Errors
Overflow Due to Host Ownership of Buffer while Receiving HDLC Message (ONR)
Overflow Due to Internal FIFO Buffer Overrun (BUFF)
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