28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 39

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 1-4.
28478-DSH-002-E
80
60
85
84
41
40
47
46
98
Pin No.
MQFP
CN8478 Hardware Signal Definitions (5 of 6)
SERR*
PERR*
DEVSEL*
IDSEL
INTA*
INTB*
REQ*
GNT*
M66EN
Pin Label
(5)
Preliminary Information / Mindspeed Proprietary and Confidential
PCI Device Select
PCI Initialization Device
Select
System Error
Parity Error
PCI MUSYCC
Interrupt
PCI Expansion Bus
Interrupt
PCI Bus Request
PCI Bus Grant
66 MHz Enable
Signal Name
Mindspeed Technologies
s/t/s I/O
s/t/s I/O
o/d O
o/d O
o/d O
t/s O
I/O
I
I
I
When asserted, DEVSEL* indicates that the driving device has decoded its
address as the target of the current cycle.
This input is used to select MUSYCC as the target for configuration read or
write cycles.
Any PCI device can assert SERR* to indicate a parity error on the address
cycle or parity error on the data cycle of a special cycle command or any
other system error where the result will be catastrophic. MUSYCC only
asserts SERR* if it detects a parity error on the address cycle.
Since SERR* is not an s/t/s signal, restoring it to the deasserted state is
done with a weak pullup (same value as used for s/t/s).
MUSYCC does not input SERR*. It is assumed that the host will reset
MUSYCC in the case of a catastrophic system error.
PERR* is asserted by the agent receiving data when it detects a parity
error on a data phase. It is asserted one clock after PAR is driven, which is
two clocks after the AD and CBE* parity was checked.
MUSYCC generates the PERR Interrupt Descriptor toward the host under
the following conditions:
MUSYCC masters a PCI cycle.
After supplying data during the data phase of the cycle, MUSYCC detects
this signal being asserted by the agent receiving the data.
MUSYCC asserts the PCI read cycle and generates the PERR Interrupt
Descriptor toward the host under the following conditions:
MUSYCC masters a PCI read cycle.
After receiving the data during the data phase of the cycle, MUSYCC
calculates that a parity error has occurred.
INTA* is driven by MUSYCC to indicate a MUSYCC Layer 2 interrupt
condition to the host processor.
INTB* is driven by MUSYCC to notify the host processor of an interrupt
pending from the EBUS.
MUSYCC drives REQ* to notify the PCI arbiter that it desires to master the
bus. Every master in the system has its own REQ*.
The PCI bus arbiter asserts GNT* when MUSYCC is free to take control of
the bus, assert FRAME*, and execute a bus cycle. Every master in the
system has its own GNT*.
ECLK speed selector. The purpose of M66EN is to allow for the EBUS to
accommodate the timing needs of slower, 33 MHz peripheral devices.
When M66EN is open or driven low ECLK is equal to PCLK (typically 66
MHz). When M66EN is driven high, ECLK is equal to PCLK divided by two
(typically 33 MHz). This input has an internal 75 KΩ pull-down resistor for
backward compatibility with Rev A or B devices. See
for the resistive pull-down current values.
®
Definition
Tables 7-3
and
7-4
26