28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 181

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

7.2.4
Illustrated in
Figure 7-13. EBUS Write/Read Transactions, Intel-Style
28478-DSH-002-E
GENERAL NOTE:
1. HLDA assertion depends on the external bus arbiter. While HOLD and HLDA are both deasserted, MUSYCC places shared EBUS
2. MUSYCC outputs valid command bus signals: EBE, ALE, RD*, and WR* 1 ECLK cycle after HLDA assertion.
3. MUSYCC outputs valid EAD address signals, 2 ECLK cycles after HLDA assertion.
4. ALE assertion occurs 3 ECLK cycles after HOLD and HLDA are both asserted.ALAPSE inserts a variable number of ECLK cycles to
5. EAD address remains valid for 1 ECLK cycle after ALE falling edge. During a write transaction, MUSYCC outputs valid EAD write data
6. ELAPSE inserts a variable number of ECLK cycles to extend RD*/WR* low pulse width and EAD data intervals. Read data inputs are
7. EAD write data and EBE byte enables remain valid for 1 ECLK cycle after RD*/WR* deassertion.
8. HOLD is deasserted, and the bus is parked (command bus deasserted, EAD tristate) 1 ECLK after RD* or WR* deassertion. The bus
9. Command bus is unparked (three-stated) one ECLK after HLDA deassertion; two different unpark phases are shown, indicating the
10. BLAPSE inserts a variable number of ECLK cycles to extend HOLD deassertion interval until the next bus request.
signals in high impedance (three-state, shown as dashed lines).
extend ALE high pulse width and EAD address interval.
1 ECLK prior to WR* assertion. During a read transaction, EAD data lines are inputs.
sampled on ECLK rising edge coincident with RD* deassertion.
parked state ends when HLDA is deasserted, 1 ECLK after RD* or WR* deassertion.
dependence on HLDA deassertion. If HLDA remained asserted until the next bus request, then command bus remains parked until 1
ECLK cycle following the next HOLD assertion. Warning: Whenever HLDA is deasserted, all shared EBUS signals are forced to three-
state after 1 ECLK cycle, regardless of whether the EBUS transaction was completed. MUSYCC will not reissue or repeat such an
aborted transaction.
Figures 7-13
8478_035
EBUS Arbitration Timing
WR* (write)
WR* (read)
RD* (write)
RD* (read)
See Notes
EAD[31:0]
EBE[3:0]*
and
HOLD
HLDA
ECLK
Preliminary Information / Mindspeed Proprietary and Confidential
ALE
7-14
are Intel- and Motorola-style write and read transactions.
Mindspeed Technologies
1
2
Byte Enables from PCI Data Phase
3
ALAPSE = 0
Address
4
5
Electrical and Mechanical Specifications
ELAPSE = 0
®
Data
6
7
8
9
BLAPSE = 0
10
168