28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 128

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

6.2.5
The service request mechanism requires that the host perform a direct memory write operation (slave write) into
the appropriate channel group’s Service Request Descriptor that is within MUSYCC’s internal registers.
The relevant references are as follows:
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6.2.6
MUSYCC has two areas of host-accessible internal memories. One is the Internal RAM (IRAM) and is accessed
through MUSYCC’s Direct Memory Access Controller (DMAC). The IRAM area contains the following descriptors
and maps:
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A second area of internal memories makes up the Host Interface registers. This area is not accessed through
MUSYCC’s DMAC. The Host Interface register contains the following descriptors:
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6.2.6.1
When all channels are deactivated, the IRAM and Host Interface registers can be read and written. The IRAM
registers require that the corresponding channel group’s line clocks (TCLK, RCLK) are active. Reading from any
IRAM register with inactive line clocks returns the pattern DEAD ACCEh—conveying "dead access." Writing to any
IRAM register with inactive line clocks returns in the writes being ignored.
Read operations to invalid (unsupported to reserved) addresses or write-only registers return all 1s. Write
operations to invalid (unsupported or reserved) addresses or read-only register bits result in the write to that bit
location being ignored.
28478-DSH-002-E
Table 5-1, MUSYCC Register Map
Table 5-9, Service Request Descriptor
Table 5-14, Transmit or Receive Time Slot Map
Table 5-16, Transmit or Receive Subchannel Map
Table 5-18, Channel Configuration Descriptor
Table 5-6, Global Configuration Descriptor
Table 5-7, Dual Address Cycle Base Pointer
Table 5-8, Group Base Pointer
Table 5-9, Service Request Descriptor
Table 5-10, Group Configuration Descriptor
Table 5-11, Memory Protection Descriptor
Table 5-12, Port Configuration Descriptor
Table 5-13, Message Length Descriptor
Table 5-14, Transmit or Receive Time Slot Map
Table 5-16, Transmit or Receive Subchannel Map
Table 5-18, Channel Configuration Descriptor
Table 5-28, Interrupt Queue Descriptor
Service Request Mechanism
MUSYCC Internal Memory
Memory Operations—Inactive Channels
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Basic Operation
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