28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 125

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

A SCR performs the following functions:
•
•
•
•
•
•
After the host requests a SCR by writing to the Service Request Descriptor, MUSYCC does not acknowledge SCR
execution with any Service Request Acknowledge (SACK) Interrupt Descriptor. Although no SACK is generated,
MUSYCC will have completed execution of the transmit and receive serial port SCR functions after two clock
pulses are applied to the respective TCLK and RCLK serial port inputs. These serial port clocks do not have to be
present when the SCR write occurs.
When writing an SCR service request, the host must ensure at least one PCI bus clock cycle has elapsed before
writing another service request. To meet this minimum elapsed service request write timing interval, it is
recommended that the host follow any SCR write with another service request read from the same address.
Reading back the Service Request Descriptor prevents a PCI burst write from sequentially writing different values
into that descriptor.
6.1.3
Every supported channel group within MUSYCC has the ability to reset (or deactivate) a specific direction for all
channels in the group using a single service request: the soft group reset service request.
When a soft group reset is requested, a direction (either transmit or receive) is specified in the request, and all
channels in the specified group and direction are deactivated. For the transmit direction, output signal TDAT is
three-stated.
The host must allow two line clock periods of the clock connected to the associated serial port to elapse for this
reset to complete before issuing another service request.
When a soft group reset is requested by the host, the service request mechanism is used. Normally, every service
request is acknowledged by MUSYCC with a SACK Interrupt Descriptor.
28478-DSH-002-E
Sets all bits to 0 in Global Configuration Descriptor register except for PORTMAP [1:0], which retains its current
value.
Sets all bits to 0 in Interrupt Status register, including NEXTINT, INTFULL, and INTCNT.
Sets all bits to 0 in Group Configuration Descriptor register except MSKCOFA and MSKOOF which are set to 1.
Thus, all supported groups (both directions) are disabled.
Resets the interrupt write index to 0. Hence, the next interrupt is written at the location pointed to by the value
of Interrupt Queue Pointer. (Present values of the Interrupt Queue Pointer and Interrupt Queue Length remain
intact.)
Deactivates all 32 channels (both directions) of each group. This action remains pending until two serial port
clocks have been applied on the respective channel group input.
Sets all bits to 0 in the following registers:
1.Port Configuration Descriptor
2.Memory Protection Descriptor
3.Message Length Descriptor
4.Service Request Descriptor
NOTE:
Soft Group Reset
Preliminary Information / Mindspeed Proprietary and Confidential
SCR does not affect any PCI configuration register contents.
Mindspeed Technologies
®
Basic Operation
112