28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 69

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Each serial interface consists of Serial Port Interfaces (SERI), Bit Level Processors (BLP), Direct Memory Access
Controllers (DMAC), and an Interrupt Controller (INTC). A separate set of SERI, BLP, and DMAC services receive
channels and transmit channels independently. A single INTC is shared by the receive and transmit BLP.
Figure 4-1
Figure 4-1.
4.1
A receive serial port interface (Rx-SERI) connects to four input signals: RCLK, RDAT, RSYNC, and ROOF. A
transmit serial port interface (Tx-SERI) connects to two input signals and one output signal, TCLK, TSYNC, and
TDAT, respectively (refer to
receiving and transmitting data bits to FIFO buffers in the BLP.
The receive and transmit data and synchronization signals are synchronous to the receive and transmit line clocks,
respectively. MUSYCC can be configured to sample in and latch out data signals and sample in status and
synchronization signals on either the rising or falling edges of the respective line clock, RCLK and TCLK. This
configuration is accomplished by setting the ROOF_EDGE, RSYNC_EDGE, RDAT_EDGE, TSYNC_EDGE, and
28478-DSH-002-E
GENERAL NOTE:
1. Channel Groups 1, 2, 3, 4, 5, 6, and 7, when supported, are identical to Group 0.
2. Bt8478 supports Channel Groups 0 through 7.
3. Bt8474 supports Channel Groups 0, 1, 2, and 3.
4. Bt8472 supports Channel Groups 0 and 1.
illustrates the serial port/host interface.
8478_013
Serial Interface Functional Block Diagram, Channel Group 0
Serial Port Interface
Rx Control
Tx Control
Interrupt
Rx Data
Tx Data
Preliminary Information / Mindspeed Proprietary and Confidential
Table 1-4, CN8478 Hardware Signal
4.0 Serial Interface
Mindspeed Technologies
Rx DMAC
Controller
Tx DMAC
Interrupt
Channel Group 0
Serial Interface
Rx Event
Tx Event
Processor
Processor
Bit Level
Bit Level
Rx
Tx
Definitions). The SERI is responsible for
®
Interface
Interface
Port
Port
Rx
Tx
Synchronization
Synchronization
Out-of-Frame
Status
Clock
Clock
Data
Data
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