CY8C3446PVI-076 Cypress Semiconductor Corp, CY8C3446PVI-076 Datasheet - Page 9

• Manufacturer Part Number: CY8C3446PVI-076
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C34xxr

Specifications of CY8C3446PVI-076

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x12b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C34
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-5
analog performance on a two-layer board.
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in
Document Number: 001-53304 Rev. *G
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with capacitance added, as shown in
page 24. The trace between the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
Figure 2-6
and
Figure 2-6
Vssd
on page 10.
Figure 2-5. Example Schematic for 100-pin TQFP Part With Power Connections
on page 10 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
Vssd
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Vddd
Vssd
C6
0.1 uF
0.1 uF
C12
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
Vddd
Vssd
PRELIMINARY
Vddd
Vssd
0.1 uF
C16
1 uF
C1
Vssd
Vddd
C2
0.1 uF
Vssd
C15
1 uF
PSoC
Vccd
Vssa
10 uF, 6.3 V
OA0-, REF0, P0[3]
C13
kHzXout, P15[2]
®
kHzXin, P15[3]
OA0out, P0[1]
OA2out, P0[0]
OA3out, P3[7]
OA1out, P3[6]
OA0+, P0[2]
SIO, P12[3]
SIO, P12[2]
SIO, P12[1]
SIO, P12[0]
3: CY8C34 Family Datasheet
Vssa
Vddio0
0.1 uF
C14
U2
CY8C55xx
P4[1]
P4[0]
Vdda
Vssd
Vssa
Vcca
NC
NC
NC
NC
NC
NC
Vddd
Vssd
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C11
0.1 uF
Figure 2-5
Vssd
Vssa
Vdda
Vcca
Vddd
Vssd
0.1 uF
C8
C9
1 uF
Vssd
Vssa
and
Vdda
Vssa
Vdda
Power System
C17
1 uF
C10
0.1 uF
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