CY8C3446PVI-076 Cypress Semiconductor Corp, CY8C3446PVI-076 Datasheet - Page 61

• Manufacturer Part Number: CY8C3446PVI-076
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C34xxr

Specifications of CY8C3446PVI-076

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x12b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C34
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11-3. AC Specifications
Document Number: 001-53304 Rev. *G
Note
F
F
Svdd
T
T
T
T
23. Based on device characterization (Not production tested).
STARTUP
SLEEP
CPU
BUSCLK
IO_INIT
HIBERNATE
Parameter
CPU frequency
Bus frequency
V
Time from V
IPOR to I/O ports set to their reset
states
Time from V
PRES to CPU executing code at
reset vector
Wakeup from sleep mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
Wakeup from sleep mode – Occur-
rence of LVD interrupt to beginning
of execution of next CPU instruction
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
DD
ramp rate
Description
DDD
DDD
[23]
/V
/V
DDA
DDA
/V
/V
1.71 V
5.5 V
3.3 V
0.5 V
CCD
CCD
0 V
/V
/V
DC
PRELIMINARY
CCA
CCA
≥
≥
Figure 11-1. F
Valid Operating Region with SMP
1.71 V ≤ V
1.71 V ≤ V
–
–
V
V
mode (12 MHz typ.)
–
–
–
CCA
DDA
Valid Operating Region
/V
/V
CPU Frequency
CCD
DDD
1 MHz
DDD
DDD
, no PLL used, IMO boot
Conditions
= regulated from
CPU
≤ 5.5 V
≤ 5.5 V
PSoC
vs. V
DD
10 MHz
®
3: CY8C34 Family Datasheet
50 MHz
Min
DC
DC
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
Max
100
50
50
10
66
12
15
1
Page 61 of 102
Units
MHz
MHz
V/ns
µs
µs
µs
µs
µs
[+] Feedback
[+] Feedback