CY8C3446PVI-076 Cypress Semiconductor Corp, CY8C3446PVI-076 Datasheet - Page 25

• Manufacturer Part Number: CY8C3446PVI-076
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C34xxr

Specifications of CY8C3446PVI-076

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x12b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C34
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note The two Vccd pins must be connected together with as
short a trace as possible. A trace under the device is
recommended, as shown in
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Note
Document Number: 001-53304 Rev. *G
Active
Alternate
Active
Sleep
Hibernate
Power Modes
14. IMO 6 MHz, CPU 6 MHz, all peripherals disabled
Active
Alternate
Active
Sleep
Hibernate <100 µs
Active
Alternate Active
Modes
Sleep
and
<15 µs
Wakeup
–
–
Table
Time
Primary mode of operation, all
peripherals available (program-
mable)
Similar to Active mode, and is
typically configured to have fewer
peripherals active to reduce
power. One possible configu-
ration is to turn off the CPU and
flash, and run peripherals at full
speed
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
6-3. The power modes allow a design to
1.2
mA
TBD
1 µA
200 nA
Current
(typ)
Description
[14]
Figure 2-6
Yes
User
defined
No
No
Execution
Code
on page 10.
PRELIMINARY
All
All
I
None
Resources
2
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
C
Digital
All
All
Comparator
None
Resources
Analog
Any interrupt
Any interrupt
Comparator,
PICU, I
CTW, LVD
PICU
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins.
between power modes.
Sleep
Hibernate
PSoC
Figure 6-5
2
C, RTC,
Clock Sources
All
All
ILO/kHzECO
None
Available
®
3: CY8C34 Family Datasheet
on page 26 illustrates the allowable transitions
Any
(programmable)
Any
(programmable)
ILO/kHzECO
Active Clocks
–
–
Comparator,
PICU, I
CTW, LVD
PICU
Wakeup Sources Reset Sources
2
C, RTC,
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled if
external regulation used.
Only hibernate regulator
active.
Regulator
All
All
XRES, LVD,
WDR
XRES
Page 25 of 102
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