CY8C3446PVI-076 Cypress Semiconductor Corp, CY8C3446PVI-076 Datasheet - Page 49

• Manufacturer Part Number: CY8C3446PVI-076
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C34xxr

Specifications of CY8C3446PVI-076

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x12b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C34
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C34,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
8.2 Delta-Sigma ADC
The CY8C34 device contains one Delta Sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for both audio signal processing
and measurement applications. The converter's nominal
operation is 12 bits at 192 ksps.
8.2.1 Functional Description
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in
connected to the internal and external buses input muxes. The
signal from the input muxes is delivered to the delta-sigma
modulator either directly or through the input buffer. The
delta-sigma modulator performs the actual analog to digital
conversion. The modulator over-samples the input and
generates a serial data stream output. This high-speed data
stream is not useful for most applications without some type of
post processing, and so is passed to the decimator through the
Analog Interface block. The decimator converts the high-speed
serial data stream into parallel ADC results. Resolution and
sample rate are controlled by the Decimator. Data is pipelined in
the decimator; the output is a function of the last four samples.
When the input multiplexer is switched, the output data is not
valid until after the fourth sample after the switch.
Figure 8-3. Delta-Sigma ADC Block Diagram
8.2.2 Operational Modes
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Fast Filter, Continuous or Fast Average.
All four modes are started by either a write to the start bit in a
control register or an assertion of the Start Of Conversion (SOC)
signal. When the conversion is complete, a status bit is set and
the output signal End Of Conversion (EOC) asserts high and
remains high until the value is read by either the DMA controller
or the CPU.
Document Number: 001-53304 Rev. *G
(Analog Routing)
Input Mux
Input Mux
Negative
Positive
Figure
Buffer
Input
8-2. Using the abus saves the analog
Table
8-3. The input buffer is
Modulator
Sigma
Delta
Figure
PRELIMINARY
Decimator
8-2,
SOC
12 Bit
Resul
EOC
8.2.2.1 Single Sample
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SOC signal to be asserted. When SOC is
signaled the ADC performs one sample conversion and captures
the result. To detect the end of conversion, the system may poll
a control register for status or configure the external EOC signal
to generate an interrupt or invoke a DMA request. When the
transfer is done the ADC reenters the standby state where it
stays until another SOC event.
8.2.2.2 Continuous
In continuous mode, the channel resets and then runs
continuously until stopped. This mode is used when the input
signal is not switched between sources and multiple samples are
required.
8.2.2.3 Fast Filter
The Fast Filter mode continuously captures signals back-to-back
and the ADC channel resets between each sample. Upon
completion of conversion of a sample, the next sample is begun
immediately. The results can be transferred either using polling,
interrupts, or a DMA request. This mode is best used when the
input is switched between multiple sources, requiring a filter
reset between each sample.
8.2.2.4 Fast FIR (Average)
This mode is similar to Fast Filter mode, but does not reset the
modulator between intermediate conversions. It is used when
decimation ratios greater than 128 are required. This mode uses
post processor sinc1 filter to perform additional decimation to
obtain resolutions greater than 16.
More information on output formats is provided in the Technical
Reference Manual.
8.2.3 Start of Conversion Input
The Start of Conversion (SOC) signal is used to start an ADC
conversion. A digital clock or UDB output can be used to drive
this input. In applications where the sampling period must be
longer than the conversion time this signal can be used. Also in
systems where the ADC needs to be synchronized to other
hardware, the SOC input is used. This signal is optional and does
not need to be connected if ADC is running in a continuous
mode.
8.2.4 End of Conversion Output
The End of Conversion (EOC) signal goes high at the end of
each ADC conversion. This signal may be used to trigger either
an interrupt or DMA request.
8.3 Comparators
The CY8C34 family of devices contains four comparators in a
device. Comparators have these features:
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (V
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low-power
PSoC
®
3: CY8C34 Family Datasheet
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