CY8C3446PVI-076 Cypress Semiconductor Corp, CY8C3446PVI-076 Datasheet - Page 46

• Manufacturer Part Number: CY8C3446PVI-076
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C34xxr

Specifications of CY8C3446PVI-076

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 25
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x12b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C34
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I
two special sets of SIO pins.
I
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
Document Number: 001-53304 Rev. *G
2
2
C provides hardware address detect of a 7-bit address without
C features include:
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
GPIO
Port
2
C pin connections are limited to the
A
N
A
L
O
G
R
O
U
T
N
G
I
Figure 8-1. Analog Subsystem Block Diagram
DAC
DAC
PRELIMINARY
Array
D SI
CM P
SC/CT Block
D istribution
Interface
Analog
C lock
CapSense Subsystem
CM P
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
Com parators
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses.
High resolution Delta-Sigma ADC.
Two 8-bit DACs that provide either voltage or current output.
Four comparators with optional connection to configurable LUT
outputs.
Two configurable switched capacitor/continuous time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer.
Two opamps for internal use and connection to GPIO that can
be used as high current output buffers.
CapSense subsystem to enable capacitive touch sensing.
Precision reference for generating an accurate analog voltage
for internal analog blocks.
PSoC
R egisters
C onfig &
CM P
SC/CT Block
Status
Reference
Precision
Decim ator
®
3: CY8C34 Family Datasheet
CM P
PH UB
A
N
A
L
O
G
R
O
U
T
N
G
I
C PU
G PIO
Port
Page 46 of 102
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