CY8C3446PVI-076 Cypress Semiconductor Corp, CY8C3446PVI-076 Datasheet
CY8C3446PVI-076
Specifications of CY8C3446PVI-076
Related parts for CY8C3446PVI-076
CY8C3446PVI-076 Summary of contents
Page 1
... AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-53304 Rev. *G PRELIMINARY ® ...
Page 2
Contents 1. Architectural Overview ..................................................... 3 2. Pinouts ............................................................................... 5 3. Pin Descriptions .............................................................. 10 4. CPU ................................................................................... 11 4.1 8051 CPU ................................................................. 11 4.2 Addressing Modes .................................................... 11 4.3 Instruction Set .......................................................... 11 4.4 DMA and PHUB ....................................................... 15 ...
Page 3
Architectural Overview Introducing the CY8C34 family of ultra low-power, flash Programmable System-on-Chip (PSoC 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C34 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination ...
Page 4
CY8C34 family these blocks can include four 16-bit timer, 2 counter, and PWM blocks slave, master, and multi-master; Full-Speed USB; and Full CAN 2.0b. For more details on the peripherals see the Peripherals” section on page 34 of ...
Page 5
The device provides a PLL to generate system clock frequencies MHz from the IMO, external crystal, or external reference clock. It also contains a separate, very low-power Internal low-speed oscillator (ILO) for the sleep and watchdog timers. ...
Page 6
P2[6] (GPIO) P2[7] (GPIO, TMS, SWDIO) P1[0] (GPIO, TCK, SWDCK) P1[1] (GPIO, Configurable XRES) P1[2] (GPIO, TDO, SWV) P1[3] (GPIO, TDI) P1[4] (GPIO, nTRST) P1[5] Notes 7. Pins are No Connect (NC) on devices without USB. NC means that ...
Page 7
P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vboost XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1 Notes 9. Pins ...
Page 8
P2[5] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] Vssb Ind Vboost Vbat Vssd XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] ...
Page 9
Figure 2-5 and Figure 2-6 on page 10 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a two-layer board. The two pins labeled Vddd must be connected together. The ...
Page 10
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0, IDAC2 Low resistance output pin for high current DACs (IDAC). OpAmp0out, OpAmp2out High current output of uncommitted opamp Extref0, Extref1 External ...
Page 11
USBIO, D+ Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are No Connect (NC) on devices without [13] USB. USBIO, D– Provides D– connection directly to a USB 2.0 bus. ...
Page 12
Instruction Set The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include: Arithmetic instructions Logical instructions Data transfer instructions Boolean instructions Program branching instructions Table 4-1. Arithmetic Instructions Mnemonic ADD ...
Page 13
Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. logical ...
Page 14
Data Transfer Instructions The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer includes transfer between any two core RAM locations or SFRs. These instructions can use direct, ...
Page 15
Table 4-4. Boolean Instructions Mnemonic CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit Complement direct bit ANL C, bit AND direct bit to carry ...
Page 16
DMA and PHUB The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of: ...
Page 17
Circular DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD. 4.4.4.5 Scatter ...
Page 18
Table 4-8. Interrupt Vector Table (continued) # Fixed Function DMA 18 Timer/Counter1 phub_termout1[2] 19 Timer/Counter2 phub_termout1[3] 20 Timer/Counter3 phub_termout1[4] 21 USB SOF Int phub_termout1[5] 22 USB Arb Int phub_termout1[6] 23 USB Bus Int phub_termout1[7] 24 USB Endpoint[0] phub_termout1[8] 25 USB ...
Page 19
Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is ...
Page 20
Figure 5-2. 8051 Internal Data Space 0x00 4 Banks, R0-R7 Each 0x1F 0x20 Bit-Addressable Area 0x2F 0x30 Lower Core RAM Shared with Stack Space (direct and indirect addressing) 0x7F 0x80 Upper Core RAM Shared Special Function Registers with Stack Space ...
Page 21
DSI. Full information on I/O ports is found in I/O System and Routing I/O ports are linked to the CPU through the PHUB and are also available in the SFRs. Using the SFRs allows faster ...
Page 22
Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin IMO 3 MHz ±1% over voltage and temperature MHzECO 4 MHz Crystal dependent DSI 0 MHz Input dependent PLL 24 MHz Input dependent Doubler 12 MHz Input dependent ILO 1 kHz ...
Page 23
The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range MHz. Its input and feedback dividers supply 4032 discrete ratios to ...
Page 24
Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found ...
Page 25
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6 on page 10. 6.2.1 Power Modes PSoC 3 devices have four different ...
Page 26
Figure 6-5. Power Mode Transitions Active Manual Sleep Buzz Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or ...
Page 27
The boost typically draws 200 µA in active mode and 12 µA in standby mode. The boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. Table 6-4 lists the boost ...
Page 28
ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when V go outside a voltage range. For AHVI, V fixed trip level. For ALVI and DLVI, V compared to trip levels ...
Page 29
No analog input, CapSense, or LCD capability Over voltage tolerance up to 5.5 V SIO can act as a general purpose analog comparator USBIO features: Full speed USB 2.0 compliant I/O Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input ...
Page 30
Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
Page 31
Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
Page 32
Resistive pull-up or resistive pull-down Resistive pull-up or pull-down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. Interfacing to ...
Page 33
LCD Segment Drive This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the “LCD Direct Drive” page 52 for details. ...
Page 34
Analog Opamp inputs and outputs High current IDAC outputs External reference inputs 6.4.19 JTAG Boundary Scan The device supports standard JTAG boundary scan chains on all I/O pins for board level test. 7. Digital Subsystem The digital programmable system creates ...
Page 35
Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C34 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features ...
Page 36
Document Number: 001-53304 Rev. *G PRELIMINARY ® PSoC 3: CY8C34 Family Datasheet Figure 7-2. PSoC Creator Framework Page 36 of 102 [+] Feedback [+] Feedback ...
Page 37
Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
Page 38
PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
Page 39
Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators ...
Page 40
Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask ...
Page 41
UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are ...
Page 42
Figure 7-12. Function Mapping Example in a Bank of UDBs 8-Bit 16-Bit Quadrature Decoder Timer PWM UDB UDB UDB UDB UDB UDB 8-Bit SPI I2C Slave 12-Bit SPI UDB UDB UDB Logic ...
Page 43
The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous ...
Page 44
CAN Features CAN2.0A/B protocol implementation – ISO 11898 compliant Standard and extended frames with bytes of data per frame Message filter capabilities Remote Transmission Request (RTR) support Programmable bit rate Mbps Listen Only ...
Page 45
USB PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. The maximum data payload size is 64 bytes for control, interrupt, and bulk endpoints and 1023 bytes ...
Page 46
I C provides hardware address detect of a 7-bit address without CPU intervention. Additionally the device can wake from low-power modes on a 7-bit hardware address match. If wakeup 2 functionality is required pin connections are limited ...
Page 47
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to ...
Page 48
ExVrefL ExVrefL1 opamp0 opamp2 swinp GPIO swfol swfol P0[4] swinn GPIO P0[5] GPIO * i0 abuf_vref_int P0[6] (1.024V) GPIO * i2 P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] P4[2] vref_cmp1 cmp1_vref (0.256V) GPIO bg_vda_res_en Vdda Vdda/2 ...
Page 49
Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C34, four in the left half (abusl [0:3]) and four in the ...
Page 50
Comparator outputs can be routed to lookup tables to perform simple logic functions and then can also be routed to digital blocks The positive input of the comparators may be optionally passed through a low pass filter. Two filters are ...
Page 51
Opamps The CY8C34 family of devices contains two general purpose opamps in a device. Figure 8-5. Opamp GPIO Analog Global Bus Opamp Analog Global Bus VREF Analog Internal Bus Analog Switch = GPIO The opamp is uncommitted and can ...
Page 52
PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain case is listed in Table 8-2. Table ...
Page 53
Figure 8-9. LCD System LCD Global DAC Clock UDB LCD Driver Block Display DMA RAM PHUB 8.6.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC ...
Page 54
Reference Source 8.9.1 Current DAC The current DAC (IDAC) can be configured for the ranges µ 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.9.2 Voltage ...
Page 55
Down Mixer The SC/CT block can be used as a mixer to down convert an input signal. This circuit is a high bandwidth passive sample network that can sample input signals MHz. This sampled value is ...
Page 56
One memory access breakpoint—break on reading or writing any memory address and data value Break on a sequence of breakpoints (non recursive) Debugging at the full speed of the CPU Debug operations are possible while the device is reset, or ...
Page 57
Development Support The CY8C34 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. 10.1 Documentation A suite of documentation, supports the CY8C34 family ...
Page 58
Electrical Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, ...
Page 59
Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog ...
Page 60
Table 11-2. DC Specifications (continued) Parameter Description [21] Sleep Mode CPU = OFF RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at [22] 1 kHz) WDT = OFF Wake ...
Page 61
Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency BUSCLK Svdd V ramp rate DD T Time from IO_INIT DDD DDA CCD IPOR to I/O ports set to their reset states T ...
Page 62
Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage ...
Page 63
Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description [27] Boost output voltage range 1.8 V 1.9 V 2 BOOST 2.7 V 3.0 V 3.3 V 3.6 V 5.0 V Load regulation Line regulation Efficiency ...
Page 64
Inputs and Outputs Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.4.1 GPIO Table 11-8. GPIO DC Specifications Parameter Description V Input voltage high threshold IH V Input voltage low ...
Page 65
SIO Table 11-10. SIO DC Specifications Parameter Description Vinref Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH Differential input mode Input voltage low threshold V GPIO ...
Page 66
Table 11-11. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 3.3 V < V < 5.5 V, Unregulated DDIO output (GPIO) mode, fast strong drive mode 1.71 V < V < 3.3 V, Unregulated DDIO output (GPIO) mode, ...
Page 67
Table 11-13. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition – Tdj2 Driver ...
Page 68
Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.5.1 Opamp Table 11-17. Opamp DC Specifications Parameter Description V Input offset voltage IOFF V Input offset voltage IOFF TCVos ...
Page 69
Delta-sigma ADC Table 11-19. 12-Bit Delta-sigma ADC DC Specifications Parameter Description [32] Resolution Number of channels – single ended – Number of channels – differential [32] Monotonicity Gain error Input offset voltage Current consumption Input voltage range – single ...
Page 70
Analog Globals Table 11-22. Analog Globals Specifications Parameter Description Rppag Resistance pin-to-pin through [34] analog global Rppmuxbus Resistance pin-to-pin through [34] analog mux bus BWag 3 dB bandwidth of analog globals CMRRag Common mode rejection for differential signals 11.5.5 ...
Page 71
IDAC Table 11-25. IDAC (Current Digital-to-analog Converter) DC Specifications Parameter Description Resolution Output current [37] High I OUT [37] Medium [37] Low INL Integral non linearity DNL Differential non linearity Ezs Zero scale error Eg Gain error IDAC_ICC DAC ...
Page 72
Table 11-28. VDAC (Voltage Digital-to-analog Converter) AC Specifications Parameter Description [38] Update rate F DAC [38] Update rate [38] Settling time to 0.5LSB [38] T High SETTLE [38] Low 11.5.8 Discrete Time Mixer The discrete time mixer is used for ...
Page 73
Transimpedance Amplifier The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-33. Transimpedance Amplifier (TIA) DC Specifications Parameter Description V Input ...
Page 74
Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-35. PGA DC Specifications Parameter Description [42] V Input ...
Page 75
Unity Gain Buffer The unity gain buffer is created using a SC/CT analog block. See the Unity Gain Buffer component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-37. Unity Gain Buffer DC ...
Page 76
LCD Direct Drive Table 11-40. LCD Direct Drive DC Specifications Parameter Description I LCD operating current CC V LCD bias range (V refers to the BIAS BIAS main output voltage(V0) of LCD DAC) LCD bias step size LCD capacitance ...
Page 77
Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.6.1 Timer Table 11-42. Timer DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 50 MHz Table 11-43. ...
Page 78
Pulse Width Modulation Table 11-46. PWM DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 50 MHz Table 11-47. Pulse Width Modulation (PWM) AC Specifications Parameter Description Operating frequency Pulse width Pulse width (external) Kill pulse width ...
Page 79
USB Table 11-52. USB DC Specifications Parameter Description Operating current 11.6.7 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so ...
Page 80
Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.7.1 Flash Table 11-54. Flash DC Specifications Parameter Description Erase and program voltage Table 11-55. Flash AC Specifications Parameter Description T ...
Page 81
Table 11-59. NVL AC Specifications Parameter Description NVL endurance NVL data retention time 11.7.4 SRAM Table 11-60. SRAM DC Specifications Parameter Description V SRAM retention voltage SRAM Table 11-61. SRAM AC Specifications Parameter Description F SRAM operating frequency SRAM 11.7.5 ...
Page 82
Table 11-62. Asynchronous Read Cycle Specifications (continued) Parameter Description Toel EM_OEn low time Toeh EM_OEn high to EM_CEn high hold time Tdoesu Data to EM_OEn high setup time Tdcesu Data to EM_CEn high setup time Tdoeh Data hold time after ...
Page 83
Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Toeld EM_ OEn EM_ Data Tadscld EM_ ADSCn Table 11-64. Synchronous Read Cycle Specifications Parameter Description T EMIF clock period Tcp EM_clock period Tceld EM_clock low to EM_CEn low Tcehd EM_clock ...
Page 84
Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Tweld EM_ WEn Tds EM_ Data Tadscld EM_ ADSCn Table 11-65. Synchronous Write Cycle Specifications Parameter Description T EMIF clock period Tcp EM_clock period Tceld EM_clock low to EM_CEn low Tcehd ...
Page 85
PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V Table 11-67. Precise power-on Reset (PRES) ...
Page 86
Interrupt Controller Table 11-71. Interrupt Controller AC Specifications Parameter Description Delay from interrupt signal input to ISR code execution from ISR code 11.8.4 JTAG Interface Table 11-72. JTAG Interface AC Specifications Parameter Description f_TCK TCK frequency T_TDI_setup TDI, TMS ...
Page 87
Clocking Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.9.1 32 kHz External Crystal Table 11-75. 32 kHz External Crystal DC Specifications Parameter Description I Operating current CC CL External ...
Page 88
Internal Low-Speed Oscillator Table 11-79. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-80. ILO AC Specifications Parameter Description Startup time Startup time Startup time Duty cycle ILO frequencies (trimmed) 100 kHz 1 kHz F ...
Page 89
Phase-Locked Loop Table 11-83. PLL DC Specifications Parameter Description I PLL operating current DD Table 11-84. PLL AC Specifications Parameter Description [53] Fpllin PLL input frequency PLL intermediate frequency [53] Fpllout PLL output frequency Lock time at startup [55] ...
Page 90
Ordering Information In addition to the features listed in Table oscillators, flash, ECC, DMA, a fixed function I and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist ...
Page 91
... Del-Sig ✔ CY8C3446LTI-085 12-bit Del-Sig CY8C3446LTI-075 ✔ 12-bit Del-Sig CY8C3446PVI-076 ✔ 12-bit Del-Sig CY8C3446PVI-102 ✔ 12-bit Del-Sig Notes 60. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See the blocks can be used. 61. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs ...
Page 92
Part Numbering Conventions PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...
Page 93
Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θJA (48-pin SSOP) Tja Package θJA (48-pin QFN) Tja Package θJA (68-pin QFN) Tja Package θJA (100-pin TQFP) Tja Package θJC ...
Page 94
Figure 13-1. 48-pin (300 mil) SSOP Package Outline 24 25 0.620 0.630 0.088 0.092 0.025 BSC TOP VIEW 7.00±0. PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE ...
Page 95
Figure 13-3. 68-pin QFN 8 × 8 with 0.4 mm Pitch Package Outline (Sawn Version) TOP VIEW 8.000±0.100 PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE ...
Page 96
Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
Page 97
Table 14-1. Acronyms Used in this Document (continued) Acronym Description PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration datasheet ...
Page 98
Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...
Page 99
Revision History ® Description Title: PSoC 3: CY8C34 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-53304 Submission Rev. ECN No. Date ** 2714270 06/03/09 *A 2758970 09/02/09 *B 2824546 12/09/09 *C 2873322 02/04/10 Document Number: 001-53304 Rev. *G PRELIMINARY ...
Page 100
Description Title: PSoC 3: CY8C34 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-53304 *D 2903576 04/01/10 Document Number: 001-53304 Rev. *G PRELIMINARY ® PSoC MKEA Updated Vb pin in PCB Schematic Updated Tstartup parameter in AC Specifications table Added ...
Page 101
Description Title: PSoC 3: CY8C34 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-53304 *E 2938381 05/27/10 *F 2958674 06/22/10 *G 2989685 08/04/10 Document Number: 001-53304 Rev. *G PRELIMINARY ® PSoC MKEA Replaced V with V in USBIO diagram and ...
Page 102
... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...