CY8C3244LTI-130 Cypress Semiconductor Corp, CY8C3244LTI-130 Datasheet - Page 61

• Manufacturer Part Number: CY8C3244LTI-130
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3244LTI-130

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 38
• Eeprom Size: 512 x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 16KB (16K x 8)
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 38
• Eeprom Memory Size: 0.5KB
• Ram Memory Size: 2KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2 Serial Wire Debug Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D– pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
Document Number: 001-56955 Rev. *K
V
2
3
1
4
PSoC 3 should be at the same voltage level as Host V
powered by V
programming. Rest of PSoC 3 voltage domains ( V
voltage level as host Programmer.
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-
pin devices, but use dedicated XRES pin for rest of devices.
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming
should be the same. XRES pin (XRES_N or P1[2]) is powered by V
powered by V
P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For
DDIO2
, V
Host Programmer
DDIO3
) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are
Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer
DDIO1
DDD
. So for Programming using the USB SWD pins with XRES pin, the V
. So V
DDIO1
SWDCK
SWDIO
XRES
of PSoC 3 should be at same voltage level as host V
V
GND
DD
GND
V
DD
DDD
, V
DD
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or programming the flash memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
. Rest of PSoC 3 voltage domains ( V
DDA
, V
DDIO0
, V
DDIO2
DDIO1
V
XRES or P1[2]
SWDCK (P1[1] or P15[7])
SWDIO (P1[0] or P15[6])
V
SSD
DDD
, V
, V
. The USB SWD pins are
, V
DDIO3
SSA
PSoC
DDA
) need not be at the same
, V
DDIO0
3, 4
DD
, V
for Port 1 SWD
®
PSoC 3
DDIO1
DDD
3: CY8C32 Family
, V
, V
DDIO2
DDIO1
DDA
, V
, V
of
DDIO3
DDIO0
Data Sheet
1, 2, 3
,
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