CY8C3244LTI-130 Cypress Semiconductor Corp, CY8C3244LTI-130 Datasheet - Page 36

• Manufacturer Part Number: CY8C3244LTI-130
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3244LTI-130

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 38
• Eeprom Size: 512 x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 16KB (16K x 8)
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 38
• Eeprom Memory Size: 0.5KB
• Ram Memory Size: 2KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 001-56955 Rev. *K
Digital Input Path
Digital Output Path
Digital Input Path
Digital Output Path
PRT[x]DR
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
Digital System Output
PRT[x]BYP
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Pin Interrupt Signal
PICU[x]INTSTAT
USBIO_CR1[4,5]
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
PRT[x]SYNC_OUT
USBIO_CR1[7]
USB SIE Control for USB Mode
Digital System Output
PRT[x]BYP
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
USB Receiver Circuitry
Pin Interrupt Signal
PICU[x]INTSTAT
Figure 6-9. SIO Input/Output Block Diagram
Figure 6-10. USBIO Block Diagram
0
1
0
1
Interrupt
Interrupt
Logic
Logic
Thresholds
In
OE
USB or I/O
In
D+ 1.5 k
D+D- 5 k
Open Drain
Drive
Logic
Buffer
Drive
Logic
Input Buffer Disable
Slew
Cntl
Vddd
Vddd
5 k
Naming Convention
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Driver
Vhigh
‘x’ = Port Number
‘y’ = Pin Number
D+ pin only
1.5 k
Vddd
Vddd
PSoC
®
PIN
3: CY8C32 Family
PIN
Data Sheet
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