CY8C3244LTI-130 Cypress Semiconductor Corp, CY8C3244LTI-130 Datasheet - Page 119

• Manufacturer Part Number: CY8C3244LTI-130
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3244LTI-130

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 38
• Eeprom Size: 512 x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 16KB (16K x 8)
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 38
• Eeprom Memory Size: 0.5KB
• Ram Memory Size: 2KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 001-56955 Rev. *K
Description Title: PSoC
Document Number: 001-56955
*K
*J
3200146
3259185
03/28/2011
05/17/2011
®
3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC
MKEA
MKEA
Removed Preliminary status from the data sheet.
Updated JTAG ID
Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table
Updated JTAG Interface AC Specifications and SWD Interface Specifications
tables
Updated USBIO DC specs
Added 0.01 to max speed
Updated Features on page 1
Added Section 5.5, Nonvolatile Latches
Updated Flash AC specs
Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables
Add reference to application note AN58304 in section 8.1
Updated 100-pin TQFP package spec
Added oscillator, I/O, VDAC, regulator graphs
Updated JTAG/SWD timing diagrams
Updated GPIO and SIO AC specs
Updated POR with Brown Out AC spec table
UpdatedIDAC graphs
Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing
diagrams
Added full chip performance graphs
Changed MHzECO range.
Added “Solder Reflow Peak Temperature” table.
Added JTAG and SWD interface connection diagrams
Updated T
Changed typ and max values for the TCVos parameter in Opamp DC
specifications table.
Updated Clocking subsystem diagram.
Changed Vssd to Vssb in the PSoC Power System diagram
Updated Ordering information.
JA
and T
JC
values in Table 13-1
PSoC
®
3: CY8C32 Family
®
)
Data Sheet
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