AD8192ACPZ-RL7 Analog Devices Inc, AD8192ACPZ-RL7 Datasheet - Page 23

• Manufacturer Part Number: AD8192ACPZ-RL7
• Description: IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8192ACPZ-RL7

• Applications: HDMI, DVI, Receivers
• Interface: I²C
• Voltage - Supply: 3.3V, 5V
• Package / Case: 56-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on
a number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. Generally, working with the PCB fabricator is
required to obtain a set of parameters to produce the desired
results.
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential pair
are close and strongly coupled, they should have a width that
produces a100 Ω differential impedance. When the traces split
apart to go into a connector, for example, and are no longer so
strongly coupled, the width of the traces needs to be increased
to yield a differential impedance of 100 Ω in the new configuration.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8192. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing dif-
ferential pairs on multiple layers, it is necessary to also reroute
the corresponding reference plane to provide one continuous
ground current return path for the differential signals. Standard
plated through-hole vias are acceptable for both the TMDS
traces and the reference plane. An example of this is illustrated
in Figure 33.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR
(REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
Figure 33. Example Routing of Reference Plane
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
THROUGH-HOLE VIAS
Rev. 0 | Page 23 of 28
TMDS Terminations
The AD8192 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the AD8192 back terminate
the output TMDS transmission lines. These back terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8192
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
The DDC and CEC signals are buffered and switched through
the AD8192, and the HPD signal is pulsed low by the AD8192.
These signals do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8192 is being used.
For example, the maximum speed of signals present on the
auxiliary lines are 100 kHz I
any layout that enables 100 kHz I
bus should suffice. The HDMI 1.3a specification, however,
places a strict 50 pF limit on the amount of capacitance that can
be measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8192, or an
equivalent receiver. There is a similar limit of 150 pF of input
capacitance for the CEC line. The benefit of the AD8192 is that
it buffers these lines, isolating the output capacitance so that
only the capacitance at the input side contributes to the speci-
fied limit. Good board design is still required, however.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
2
C data on the DDC lines, therefore,
2
C to be passed over the DDC
AD8192