AD8192ACPZ-RL7 Analog Devices Inc, AD8192ACPZ-RL7 Datasheet - Page 16

IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC

AD8192ACPZ-RL7

Manufacturer Part Number
AD8192ACPZ-RL7
Description
IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8192ACPZ-RL7

Applications
HDMI, DVI, Receivers
Interface
I²C
Voltage - Supply
3.3V, 5V
Package / Case
56-LFCSP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD8192
READ PROCEDURE
To read data from the AD8192 register set, an I
as a microcontroller) needs to send the appropriate control
signals to the AD8192 slave device. The signals are controlled
by the I
the procedure, see Figure 29. The steps for a read procedure are
as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for the AD8192 to acknowledge the request.
11. Capture the data from the AD8192.
GENERAL CASE
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the AD8192 part address (seven bits). The upper six
bits of the AD8192 part address are the static value
[100100], and the LSB is set by Input Pin I2C_ADDR. This
transfer should be MSB first.
Send the write indicator bit (0).
Wait for the AD8192 to acknowledge the request.
Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.
Wait for the AD8192 to acknowledge the request.
Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.
Resend the AD8192 part address (seven bits) from Step 2.
The upper six bits of the AD8192 part address compose the
static value [100100]. The LSB is set by Input Pin I2C_ADDR.
This transfer should be MSB first.
Send the read indicator bit (1).
The AD8192 serially transfers the data (eight bits) held in
the register indicated by the address set in Step 5. This data
is sent MSB first.
EXAMPLE
I2C_SDA
I2C_SDA
I2C_SCL
2
C master unless otherwise specified. For a diagram of
START
1
FIXED PART
2
ADDR
ADDR
R/W
3
ACK
4
2
C master (such
5
REGISTER ADDR
Figure 29. I
Rev. 0 | Page 16 of 28
2
C Read Procedure
ACK
6
7
SR
12. Do one of the following:
a.
b.
c.
d.
FIXED PART
8
ADDR
Send a no acknowledge followed by a stop condition
(while holding the I2C_SCL line high, pull the SDA
line high) and release control of the bus to end the
transaction (shown in Figure 29).
Send a no acknowledge followed by a repeated start
condition (while holding the I2C_SCL line high, pull
the I2C_SDA line low) and continue with Step 2 of the
write procedure (see the previous Write Procedure
section) to perform a write.
Send a no acknowledge followed by a repeated start
condition (while holding the I2C_SCL line high, pull
the I2C_SDA line low) and continue with Step 2 of
this procedure to perform a read from another
address.
Send a no acknowledge followed by a repeated start
condition (while holding the I2C_SCL line high, pull
the I2C_SDA line low) and continue with Step 8 of
this procedure to perform a read from the same
address.
ADDR
R/W
9 10 11
ACK
DATA
NACK
12
STOP
13

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