AD8192ACPZ-RL7 Analog Devices Inc, AD8192ACPZ-RL7 Datasheet - Page 19

• Manufacturer Part Number: AD8192ACPZ-RL7
• Description: IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8192ACPZ-RL7

• Applications: HDMI, DVI, Receivers
• Interface: I²C
• Voltage - Supply: 3.3V, 5V
• Package / Case: 56-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TRANSMITTER SETTINGS REGISTER
TX_PE[x]: High Speed (TMDS) Output Pre-Emphasis Level
Select Bus (For All TMDS Channels)
Table 20. TX_PE[x] Description
TX_PE[x]
00b
01b
10b
11b
TX_PTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All Channels)
Table 21. TX_PTO Description
TX_PTO
0b
1b
TX_OCL: High Speed (TMDS) Output Current Level Select
Bit (For All Channels)
Table 22. TX_OCL Description
TX_OCL
0b
1b
SOURCE SIGN CONTROL REGISTER
A_SG[x]: High Speed (TMDS) Input A, Channel x Sign
Select Bits
Defines the input/input complement polarity of the Channel x.
Table 23. A_SG[x] Description
A_SG[x]
0b
1b
Table 24. A_SG[x] Mapping
A_SG[x]
0b
1b
OP[x]
IP_A[x]
IN_A[x]
Description
Output termination off
Output termination on
Description
Output current set to 10 mA
Output current set to 20 mA
Description
Channel sign is positive
Channel sign is inverted
Description
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
ON[x]
IN_A[x]
IP_A[x]
Rev. 0 | Page 19 of 28
B_SG[x]: High Speed (TMDS) Input B, Channel x Sign
Select Bits
These bits define the input/input complement polarity of the
Channel x.
Table 25. B_SG[x] Description
B_SG[x]
0b
1b
Table 26. B_SG[x] Mapping
B_SG[x]
0b
1b
SOURCE A INPUT/OUTPUT MAPPING REGISTER
A[x]_HS_MAP[1:0]: High Speed (TMDS) Input A, Output
Channel x, Select Bits
These bits define the input/output mapping of the high speed
channels when Source A is selected.
Table 27. A[x]_HS_MAP[1:0] Mapping
A[x]_HS_MAP[1:0]
00b
01b
10b
11b
SOURCE B INPUT/OUTPUT MAPPING REGISTER
B[x]_HS_MAP[1:0]: High speed (TMDS) Input B, Output
Channel x, Select Bits
These bits define the input/output mapping of the high speed
channels when Source B is selected.
Table 28. B[x]_HS_MAP[1:0] Mapping
B[x]_HS_MAP[1:0]
00b
01b
10b
11b
OP[x]
IP_B[x]
IN_B[x]
Description
Channel sign is positive
Channel sign is inverted
A0
A1
A2
A3
O[x]
B0
B1
B2
B3
O[x]
ON[x]
IN_B[x]
IP_B[x]
AD8192