AD8192ACPZ-RL7 Analog Devices Inc, AD8192ACPZ-RL7 Datasheet - Page 18

• Manufacturer Part Number: AD8192ACPZ-RL7
• Description: IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8192ACPZ-RL7

• Applications: HDMI, DVI, Receivers
• Interface: I²C
• Voltage - Supply: 3.3V, 5V
• Package / Case: 56-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8192
HIGH SPEED DEVICE MODES REGISTER
HS_EN: High Speed (TMDS) Switch Enable Bit
Table 10. HS_EN Description
HS_EN
0b
1b
HS_CH: High Speed (TMDS) Source Select Bit
Table 11. HS_CH Mapping
HS_CH
0b
1b
AUXILIARY DEVICE MODES REGISTER
AUX_LK: Auxiliary (Low Speed) Switch Mode Lock Bit
Table 12. AUX_LK Description
AUX_LK
0b
1b
AUX_EN: Auxiliary (Low Speed) Switch Enable Bit
Table 13. AUX_EN Description
AUX_EN
0b
1b
AUX_CH: Auxiliary (Low Speed) Switch Source Select Bit
Table 14. AUX_CH Mapping
AUX_CH
0b
1b
RECEIVER SETTINGS REGISTER
RX_TO: High Speed (TMDS) Input Termination Mode
Control Select Bit
Table 15. RX_TO Description
RX_TO
0b
1b
Description
High speed channels off, low power/standby mode
High speed channel on
Description
Input termination mode is manual, individual
terminations can be enabled/disabled according to
settings in the input termination pulse register
Input termination for TMDS Channel x is always
connected
O[3:0]
A[3:0]
B[3:0]
Description
Auxiliary switch lock off, auxiliary source is switched
independently of the high speed source
Auxiliary switch lock on, auxiliary switch source select
is slaved to the high speed switch source select bit
Description
Auxiliary switch off, no low speed input/output to
low speed common input/output connection
Auxiliary switch on
AUX_COM[3:0]
AUX_A[3:0]
AUX_B[3:0]
Description
High Speed Source A switched to output
High Speed Source B switched to output
Description
Auxiliary Source A switched to
output
Auxiliary Source B switched to
output
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INPUT TERMINATION CONTROL REGISTER
RX_PT[x]: High Speed (TMDS) Input Termination x,
Select Bit
Table 16. RX_PT[x] Description
RX_PT[x]
0b
1b
Table 17. RX_PT[x] Mapping
RX_PT[x]
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RECEIVE EQUALIZER REGISTER
RX_EQ[x]: High Speed (TMDS) Input x, Equalization Level
Select Bit
Table 18. RX_EQ[x] Description
RX_EQ[x]
0b
1b
Table 19. RX_EQ[x] Mapping
RX_EQ[x]
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Description
Input termination mode for TMDS Channel x is
always disconnected
Input termination for TMDS Channel x is always
connected
Corresponding Input TMDS Channel
Corresponding Input TMDS Channel
A0
A1
A2
A3
B3
B2
B1
B0
A0
A1
A2
A3
B3
B2
B1
B0
Description
Low equalization (6 dB)
High equalization (12 dB)