AD8192 AD [Analog Devices], AD8192 Datasheet

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... OR technique. The AD8192 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. The AD8192 is available in a space-saving, 56-lead LFCSP surface-mount, lead-free plastic package specified to operate over the −40°C to +85°C temperature range. ...

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... AD8192 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application ........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 12 Input Channels ............................................................................ 12 Output Channels ........................................................................ 12 Switching Mode .......................................................................... 13 Pre-Emphasis .............................................................................. 13 Auxiliary Multiplexer ...

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... Single-ended Conditions/Comments DC bias = 2 voltage = 3 100 kHz 10% to 90%, no capacitive load 90 400 pF LOAD DC bias = 1. voltage = 2 100 kHz kΩ to +3.3 V PULLUP Rev Page AD8192 Min Typ Max 2.25 − 150 1200 AVCC − ...

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... Serial interface Assumes that the unselected HDMI/DVI link is deactivated through the hot plug detect line, as required by the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a. 2 The AD8192 slave and its control interface is based on the 3 Conditions/Comments 10 1500 pF kΩ ...

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... JEDEC circuit board for surface-mount packages. θ < AVCC + 0.6 V circuit board with no airflow. IN Table 5. Thermal Resistance < AMUXVCC + 0.6 V Model IN < DVCC + 0.6 V 56-Lead LFCSP IN ESD CAUTION Rev Page specified for the exposed pad soldered to the JC θ θ 2.1 AD8192 Unit °C/W ...

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... AD8192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE AD8192 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE Table 6. Pin Function Descriptions Pin No. Mnemonic 1, 10, 33, 42 AVCC 2 IN_A0 3 IP_A0 4, 13, 30, 39, ePAD AVEE 5 IN_A1 6 IP_A1 7, 36 VTTI 8 IN_A2 9 IP_A2 11 IN_A3 12 IP_A3 14 I2C_ADDR 15, 21 ...

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... Display Data Channel Common Input/Output. Reference Positive Auxiliary Switch Supply Source Side. Power Negative Digital and Auxiliary Switch Power Supply nominal. LS I/O Consumer Electronics Control Input/Output Hot Plug Detect Output. LS I/O Display Data Channel Input/Output. LS I/O Display Data Channel Input/Output. Rev Page AD8192 ...

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... GENERATOR TP1 TP2 Figure 4. Test Circuit Diagram for Rx Eye Diagrams Figure 7. Rx Eye Diagram at TP3 (Cable = AWG) Figure 8. Rx Eye Diagram at TP3 (Cable = AWG) Rev Page AD8192 SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP3 ...

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... TP2 Figure 9. Test Circuit Diagram for Tx Eye Diagrams Figure 12. Tx Eye Diagram at TP3 (Cable = AWG) Figure 13. Tx Eye Diagram at TP3 (Cable = AWG) Rev Page HDMI CABLE SERIAL DATA ANALYZER TP3 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps AD8192 7 − 1, ...

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... AD8192 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 A data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 0.6 0.5 0.4 0.3 1.5Gbps, 2.25Gbps 12dB EQ = 12dB 0.2 0.1 ALL CABLES = 24 AWG CABLE LENGTH (m) Figure 14 ...

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... Rev Page DJ 12dB 45 RJ 12dB 2.5 2.7 2.9 3.1 3.3 INPUT COMMON-MODE VOLTAGE (V) Figure 23. Jitter vs. Input Common-Mode Voltage 100 OUTPUT 50 INPUT –40 – TEMPERATURE (°C) Figure 24. Single-Ended Termination Resistance vs. Temperature AD8192 7 − 1, 3.5 3 ...

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... RX_EQ bits in the receive equalizer register. No specific cable length is suggested for a particular equalization setting because cable performance varies widely among manufacturers; however, in general, the equalization of the AD8192 can be set without degrading the signal integrity, even for short input cables. VTTI IP ...

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... SWITCHING MODE The AD8192 is a 2:1 HDMI/DVI source switch. The user can select which high speed TMDS input is routed to the output by programming the HS_CH bit of the high speed modes register and ...

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... This prevents contention on the DDC bus, enabling a design to include an EDID upstream of the AD8192. DDC LOGIC LEVELS The AD8192 supports the use of flexible (3 logic levels on the DDC bus. The logic level for the DDC_A and DDC_B buses are set by the voltage on VREF_AB, and the logic level for the DDC_COM bus is set by the voltage on VREF_COM ...

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... SERIAL CONTROL INTERFACE RESET On initial power-up any point during operation, the AD8192 register set can be restored to the default values by pulling the RESET pin to low according to the specification in Table 1. During normal operation, however, the must be pulled up to 3.3 V. WRITE PROCEDURE To write data to the AD8192 register set microcontroller) needs to send the appropriate control signals to the AD8192 slave device ...

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... I2C_SCL line high and pulling the I2C_SDA line low. 8. Resend the AD8192 part address (seven bits) from Step 2. The upper six bits of the AD8192 part address compose the static value [100100]. The LSB is set by Input Pin I2C_ADDR. This transfer should be MSB first. ...

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... CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I 2 least significant bit of the AD8192 I C part address is set by tying the Pin I2C_ADDR to 3.3 V (I2C_ADDR = 1b (I2C_ADDR = 0b). Table 9. Register Map Name Bit 7 Bit 6 High High speed ...

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... AD8192 HIGH SPEED DEVICE MODES REGISTER HS_EN: High Speed (TMDS) Switch Enable Bit Table 10. HS_EN Description HS_EN Description 0b High speed channels off, low power/standby mode 1b High speed channel on HS_CH: High Speed (TMDS) Source Select Bit Table 11. HS_CH Mapping HS_CH O[3:0] Description 0b A[3:0] High Speed Source A switched to output ...

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... Channel x, Select Bits These bits define the input/output mapping of the high speed channels when Source B is selected. Table 28. B[x]_HS_MAP[1:0] Mapping B[x]_HS_MAP[1:0] 00b 01b ON[x] 10b 11b IN_A[x] IP_A[x] Rev Page AD8192 Description Channel sign is positive Channel sign is inverted OP[x] ON[x] IP_B[x] IN_B[x] IN_B[x] IP_B[x] O[ ...

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... This allows a designer to integrate the AD8192 into virtually any application without requiring the use of vias on the TMDS traces in the PCB layout. In addition input equalization, the AD8192 provides output pre-emphasis that boosts the output TMDS +5V +3.3V ...

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... As such, specific cable types and lengths are not recommended for use with a particular equalizer setting. In nearly all applica- tions, the AD8192 equalization level can be set to high dB, for all input cable configurations at all data rates, without degrading the signal integrity. ...

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... PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8192, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. ...

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... SDA or SCL at the HDMI input connector. This 50 pF limit includes the HDMI connector, the PCB, and whatever capacitance is seen at the input of the AD8192 equivalent receiver. There is a similar limit of 150 pF of input capacitance for the CEC line. The benefit of the AD8192 is that ...

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... When the AD8192 is powered off, all DDC/CEC inputs are placed in a high impedance state. This prevents contention on the DDC bus, enabling a design to include an EDID in front of the AD8192. Power Supplies The AD8192 has five separate power supplies referenced to two separate grounds. The supply/ground pairs are • ...

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... SEATING PLANE * NOTE: THE AD8192 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL HDMI/DVI TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO AVEE RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG ...

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... AD8192 NOTES Rev Page ...

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... NOTES Rev Page AD8192 ...

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... AD8192 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...