CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 67

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

DS680F1
6.31
6.31.1 Limiter Attack Rate
6.32
6.32.1 ALCx Enable
6.32.2 ALC Attack Rate
Reserved
ALCB
7
7
Limiter Attack Rate (Address 29h)
ALC Enable & Attack Rate (Address 2Ah)
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page
Note:
the DIGSFT
the respective disable bit
page
Configures the automatic level controller.
Note:
Sets the rate at which the ALC applies analog and/or digital attenuation from levels above the AMAX[2:0]
threshold
Note:
the ANLGSFTx
page
Cross Disable” on page
LIMARATE[5:0]
00 0000
···
11 1111
Application:
ALC
0
1
Application:
LIMARATE[5:0]
00 0000
···
11 1111
Application:
66) is enabled.
49) setting unless the respective disable bit
Reserved
ALCA
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
The ALC is not available in passthrough mode.
The ALC attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
(“ALC Maximum Threshold” on page
6
6
(“Digital Soft Ramp” on page
(“Ch. x Analog Soft Ramp” on page
Attack Time
Fastest Attack
···
Slowest Attack
“Limiter” on page 31
ALC Status
Disabled
Enabled
“Automatic Level Control (ALC)” on page 27
Attack Time
Fastest Attack
···
Slowest Attack
“Automatic Level Control (ALC)” on page 27
ALCARATE5
LIMARATE5
56) is enabled.
5
5
(“Limiter Soft Ramp Disable” on page 65
AALCRATE4
LIMARATE4
4
4
65).
53) and DIGZC
5/13/08
68).
ALCARATE3
LIMARATE3
(“ALCx Soft Ramp Disable” on page 55
49) and ANLGZCx
3
3
(“Digital Zero Cross” on page
ALCARATE2
LIMARATE2
2
2
or
“Limiter Zero Cross Disable” on
(“Ch. x Analog Zero Cross” on
ALCARATE1
LIMARATE1
1
1
53) setting unless
or
CS42L52
ALCARATE0
LIMARATE0
“ALCx Zero
0
0
67