CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 44

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

44
6.4
6.4.1
6.4.2
6.5
6.5.1
PDN_HPB1
AUTO
7
7
Power Control 3 (Address 04h)
Clocking Control (Address 05h)
Headphone Power Control
Configures how the SPKR/HP pin, 31, controls the power for the headphone amplifier.
Speaker Power Control
Configures how the SPKR/HP pin, 31, controls the power for the speaker amplifier.
Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a
slave.
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. When AUTO is disabled and the CODEC operates in master mode, the MCLKDIV2 bit is ignored.
3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
PDN_HPx[1:0]
00
01
10
11
PDN_SPKx[1:0]
00
01
10
11
AUTO
0
1
Application:
(“32kHz Sample Rate Group” on page
page
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
PDN_HPB0
SPEED1
45) and RATIO[1:0] bits
6
6
Headphone Status
Headphone channel is ON when the SPKR/HP pin, 31, is LO.
Headphone channel is OFF when the SPKR/HP pin, 31, is HI.
Headphone channel is ON when the SPKR/HP pin, 31, is HI.
Headphone channel is OFF when the SPKR/HP pin, 31, is LO.
Headphone channel is always ON.
Headphone channel is always OFF.
Speaker Status
Speaker channel is ON when the SPKR/HP pin, 31, is LO.
Speaker channel is OFF when the SPKR/HP pin, 31, is HI.
Speaker channel is ON when the SPKR/HP pin, 31, is HI.
Speaker channel is OFF when the SPKR/HP pin, 31, is LO.
Speaker channel is always ON.
Speaker channel is always OFF.
Auto-detection of Speed Mode
Disabled
Enabled
“Serial Port Clocking” on page 34
PDN_HPA1
SPEED0
5
5
(“Internal MCLK/LRCK Ratio” on page
32k_GROUP
PDN_HPA0
4
4
45) and/or the VIDEOCLK bit
5/13/08
PDN_SPKB1
VIDEOCLK
3
3
PDN_SPKB0
RATIO1
2
2
45). Low sample rates may also
(“27 MHz Video Clock” on
PDN_SPKA1
RATIO0
1
1
CS42L52
PDN_SPKA0
MCLKDIV2
DS680F1
0
0