CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 33

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

DS680F1
4.4.2
4.5
4.5.1
4.5.2
PWM Outputs
Overriding the PGA Power Down
To accommodate automatic activation of the headphone amplifier when the SPK/HP_SW switch pin
changes, the CS42L52 will automatically power up the PGA whenever passthrough is enabled, regard-
less of the PDN_PGA setting. Refer to the table below for details on how this PGA power-down override
functions in accordance with the state of the headphone channels. The shaded cells represent normal
PGA operation when passthrough is disabled.
When passthrough is enabled, turning the headphone channel ON (by writing ‘11’b to HPx_PDN[1:0] or
by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically disable the
PGAx_PDN in order to transmit the analog signal to the headphone.
Mono Speaker Output Configuration
The CS42L52 accommodates a stereo as well as a mono speaker output configuration. In mono mode
the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speak-
er. Refer to the table below for pin mapping in mono configuration.
VP Battery Compensation
The CS42L52 provides the option to maintain a desired power output level, independent of the VP supply.
When enabled, this feature works by monitoring the voltage on the VP supply and reducing the attenua-
tion on the speaker outputs when VP voltage levels fall.
Note:
based on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.
Referenced Control
PDN_ADCx .........................
PASSTHRU .........................
PDN_OVRD ........................
SPKx_PDN[1:0]...................
Referenced Control
PDN_PGAx .........................
PASSTHRU .........................
HPx_PDN[1:0].....................
Referenced Control
SPKMONO..........................
SPKSWAP...........................
PDN_PGA
Pin
4
6
7
9
The internal ADC that monitors the VP supply operates from the VA supply. Calculations are
0
1
SPKSWAP=0
SPKOUTB+
SPKOUTA+
SPKOUTA-
SPKOUTB-
Register Location
“Power Down ADCx” on page 43
“Passthrough Analog” on page 52
“Power Down ADC Override” on page 43
“Speaker Power Control” on page 44
Register Location
“Power Down PGAx” on page 42
“Passthrough Analog” on page 52
“Headphone Power Control” on page 44
Register Location
“Speaker MONO Control” on page 54
“Speaker Channel Swap” on page 54
PASSTHRU
SPKMONO=0
x
0
1
5/13/08
SPKSWAP=1
SPKOUTB+
SPKOUTA+
SPKOUTB-
SPKOUTA-
Speaker Output
HP Channel
OFF
ON
x
x
SPKSWAP=0
SPKOUTA+
SPKOUTA+
SPKOUTA-
SPKOUTA-
Powered UP
Powered DOWN
Powered DOWN
Powered UP
SPKMONO=1
PGA Status
SPKSWAP=1
SPKOUTB+
SPKOUTB+
SPKOUTB-
SPKOUTB-
CS42L52
33