CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 53

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

DS680F1
6.13.4 HP/Speaker De-emphasis
6.13.5 Digital Soft Ramp
6.13.6 Digital Zero Cross
Configures a 15µs/50µs digital de-emphasis filter response on the headphone/line and speaker outputs
Configures an incremental volume ramp from the current level to the new level at the specified rate.
Notes:
1. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
Configures when the signal level changes occur for the digital volume controls.
Notes:
1. If the signal does not encounter a zero crossing, the requested volume change will occur after a
2. The zero cross function is independently monitored and implemented for each channel.
3. The DIS_LIMSFT bit
4. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
DEEMPHASIS
0
1
DIGSFT
0
1
Ramp Rate:
DIGZC
0
1
occur with a soft ramp only when
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).
occur on a zero crossing only when
Control Port Status
Disabled
Enabled
Volume Changes
Do not occur with a soft ramp
Occur with a soft ramp
1/8 dB every LRCK cycle
Volume Changes
Do not occur on a zero cross-
ing
Occur on a zero crossing
(“Limiter Soft Ramp Disable” on page
bits 7 and 6 in register 29h are set to ‘00’b.
bits 7 and 6 in register 29h are set to ‘00’b.
Affected Digital Volume Controls
MSTxMUTE
HPxMUTE, SPKxMUTE
ADCxVOL[7:0]
AMIXxMUTE, AMIXxVOL[7:0]
PMIXxMUTE, PMIXxVOL[7:0]
MSTxVOL[7:0]
HPxVOL[7:0]
SPKxVOL[7:0]
ALC and Limiter Attack/Release
Beep Volume
Affected Digital Volume Controls
MSTxMUTE
AMIXxMUTE, AMIXxVOL[7:0]
PMIXxMUTE, PMIXxVOL[7:0]
MSTxVOL[7:0]
ALC and Limiter Attack/Release
Beep Volume
5/13/08
(“Master Playback Mute” on page
(“Master Playback Mute” on page
(“Headphone Volume Control” on page
(“Beep Volume” on page
(“Beep Volume” on page
(“Speaker Volume Control” on page
(“ADCx Volume” on page
(“Master Volume Control” on page
(“Master Volume Control” on page
(“Playback Control 2 (Address 0Fh)” on page
65) is ignored when zero cross is enabled.
(“PCM Mixer Channel x Volume” on page
(“PCM Mixer Channel x Volume” on page
(“ADC Mixer Channel x Volume” on page
(“ADC Mixer Channel x Volume” on page
(page 66
(page 66
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CS42L52
54),
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53
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