CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 6

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

6
7. ANALOG PERFORMANCE PLOTS .................................................................................................... 74
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 76
6.25 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h) ....................................... 63
6.26 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h) ..................................... 63
6.27 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h) ...................................... 64
6.28 ADC & PCM Channel Mixer (Address 26h) .................................................................................. 64
6.29 Limiter Control 1, Min/Max Thresholds (Address 27h) ................................................................. 65
6.30 Limiter Control 2, Release Rate (Address 28h) ............................................................................ 66
6.31 Limiter Attack Rate (Address 29h) ................................................................................................ 67
6.32 ALC Enable & Attack Rate (Address 2Ah) ................................................................................... 67
6.33 ALC Release Rate (Address 2Bh) ................................................................................................ 68
6.34 ALC Threshold (Address 2Ch) ..................................................................................................... 68
6.35 Noise Gate Control (Address 2Dh) ............................................................................................... 69
6.36 Status (Address 2Eh) (Read Only) ............................................................................................... 70
6.37 Battery Compensation (Address 2Fh) .......................................................................................... 71
6.38 VP Battery Level (Address 30h) (Read Only) ............................................................................... 72
6.39 Speaker Status (Address 31h) (Read Only) ................................................................................. 72
6.40 Charge Pump Frequency (Address 34h) ...................................................................................... 73
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 74
8.1 Auto Detect Enabled ....................................................................................................................... 76
6.24.2 Bass Gain ............................................................................................................................ 63
6.25.1 Master Volume Control ........................................................................................................ 63
6.26.1 Headphone Volume Control ................................................................................................ 63
6.27.1 Speaker Volume Control ..................................................................................................... 64
6.28.1 PCM Mix Channel Swap ..................................................................................................... 64
6.28.2 ADC Mix Channel Swap ...................................................................................................... 64
6.29.1 Limiter Maximum Threshold ................................................................................................ 65
6.29.2 Limiter Cushion Threshold .................................................................................................. 65
6.29.3 Limiter Soft Ramp Disable ................................................................................................... 65
6.29.4 Limiter Zero Cross Disable .................................................................................................. 66
6.30.1 Peak Detect and Limiter ...................................................................................................... 66
6.30.2 Peak Signal Limit All Channels ........................................................................................... 66
6.30.3 Limiter Release Rate ........................................................................................................... 66
6.31.1 Limiter Attack Rate .............................................................................................................. 67
6.32.1 ALCx Enable ....................................................................................................................... 67
6.32.2 ALC Attack Rate .................................................................................................................. 67
6.33.1 ALC Release Rate ............................................................................................................... 68
6.34.1 ALC Maximum Threshold .................................................................................................... 68
6.34.2 ALC Minimum Threshold ..................................................................................................... 69
6.35.1 Noise Gate All Channels ..................................................................................................... 69
6.35.2 Noise Gate Enable .............................................................................................................. 69
6.35.3 Noise Gate Threshold and Boost ........................................................................................ 70
6.35.4 Noise Gate Delay Timing .................................................................................................... 70
6.36.1 Serial Port Clock Error (Read Only) .................................................................................... 70
6.36.2 DSP Engine Overflow (Read Only) ..................................................................................... 71
6.36.3 PCMx Overflow (Read Only) ............................................................................................... 71
6.36.4 ADCx Overflow (Read Only) ............................................................................................... 71
6.37.1 Battery Compensation ......................................................................................................... 71
6.37.2 VP Monitor ........................................................................................................................... 71
6.37.3 VP Reference ...................................................................................................................... 72
6.38.1 VP Voltage Level (Read Only) ............................................................................................ 72
6.39.1 Speaker Current Load Status (Read Only) ......................................................................... 72
6.39.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 73
6.40.1 Charge Pump Frequency .................................................................................................... 73
5/13/08
CS42L52
DS680F1