CDB42L52 Cirrus Logic Inc, CDB42L52 Datasheet - Page 45

• Manufacturer Part Number: CDB42L52
• Description: Eval Bd LP Codec W/Class D Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L52
• Primary Attributes: 4 Stereo Audio Inputs, Stereo Line and Speaker Outputs, S/PDIF Inputs and Outputs
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42L52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1505

DS680F1
6.5.2
6.5.3
6.5.4
6.5.5
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
Notes:
1. Slave/Master Mode is determined by the M/S bit in
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
3. These bits are ignored when the AUTO bit
32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
32kGROUP
0
1
Application:
VIDEOCLK
0
1
Application:
SPEED[1:0]
00
01
10
11
Application:
RATIO[1:0]
00
01
10
11
Application:
(“32kHz Sample Rate Group” on page
page
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
45) and RATIO[1:0] bits
Slave Mode
Serial Port Speed
Double-Speed Mode (DSM - 50 kHz -100 kHz Fs)
Single-Speed Mode (SSM - 4 kHz -50 kHz Fs)
Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs)
Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)
“Serial Port Clocking” on page 34
8 kHz, 16 kHz or 32 kHz sample rate?
No
Yes
“Serial Port Clocking” on page 34
27 MHz MCLK?
No
Yes
“Serial Port Clocking” on page 34
Internal MCLK Cycles per LRCK
128
125
132
136
“Serial Port Clocking” on page 34
(“Internal MCLK/LRCK Ratio” on page
45) and/or the VIDEOCLK bit
5/13/08
(“Auto-Detect” on page
“Master/Slave Mode” on page
Master Mode
MCLK/LRCK Ratio
512
256
128
128
SCLK/LRCK Ratio in Master Mode
64
62
66
68
44) is enabled.
45). Low sample rates may also
(“27 MHz Video Clock” on
SCLK/LRCK Ratio
64
64
64
64
46.
CS42L52
45