IPR-FFT Altera, IPR-FFT Datasheet - Page 9

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–4. Performance with the Streaming Data Flow Engine Architecture—Cyclone III Devices
Table 1–5. Performance with the Variable Streaming Data Flow Engine Architecture—Cyclone III Devices
Table 1–6. Resource Usage with Buffered Burst Data Flow Architecture—Cyclone III Devices (Part 1 of 2)
© December 2010 Altera Corporation
Note to
(1) EP3C40F780C6 device.
Floating
Floating
Floating
Note to
(1) EP3C40F780C6 device.
(2) EP3C55F780C6 device.
Point Type
4096
Points
1024
1024
256
256
1024
Points
256
Fixed
Fixed
Fixed
4096
(1)
(2)
(3)
Table
Table
(2)
(3)
(1)
(2)
(2)
1–4:
1–5:
Combinational
Points
1024
4096
1024
4096
1
256
256
Engines
Number of
3437
3857
3719
LUTs
1
1
1
2
2
Table 1–5
and bit-reversed outputs, for width 16 (32 for floating point), for Cyclone III
(EP3C16F484C6) devices.
The variable streaming with fixed-point number representation uses natural word
growth, therefore the multiplier requirement is larger compared with the equivalent
streaming FFT with the same number of points.
If you want to significantly reduce M9K memory utilization, set a lower f
Table 1–6
multipliers /2 adders complex multiplier structure, for data and twiddle width 16, for
Cyclone III (EP3C25F324C6) devices.
Combinational
(1)
20771
26573
32428
3859
5243
6725
LUTs
Combinational
Registers
Logic
shows the variable streaming data flow performance, with in order inputs
lists resource usage with buffered burst data flow architecture, using the 4
3906
4650
4734
3129
3234
3291
5161
5270
LUTs
Registers
14158
17540
20939
Logic
4373
5840
7369
Memory
155904
622848
39168
(Bits)
Registers
Logic
3778
3976
4160
5961
6169
Memory
170335
140410
568163
41940
34464
(Bits)
9997
Memory
(M9K)
20
20
76
Memory
123136
491776
123136
30976
30,76
(Bits)
Memory
(M9K)
148
15
21
40
62
93
Blocks
9 × 9
24
24
24
Blocks
9 × 9
128
160
Memory
40
56
72
96
(M9K)
16
16
60
31
31
(MHz)
231
244
234
f
MAX
(MHz)
191
193
198
116
116
116
f
FFT MegaCore Function User Guide
MAX
Blocks
9 × 9
Count
24
24
24
48
48
Clock
Cycle
1024
4096
256
Count
Clock
Cycle
1024
4096
1024
4096
256
256
MAX
Transform
Time (μs)
Transform
Time (μs)
17.52
target.
(MHz)
1.11
4.19
20.67
247
241
227
225
207
f
1.34
5.29
2.20
8.83
35.3
MAX
1–5