IPR-FFT Altera, IPR-FFT Datasheet - Page 10

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–6
Table 1–6. Resource Usage with Buffered Burst Data Flow Architecture—Cyclone III Devices (Part 2 of 2)
Table 1–7. Performance with the Buffered Burst Data Flow Architecture—Cyclone III Devices
Table 1–8. Resource Usage with the Burst Data Flow Architecture—Cyclone III Devices
FFT MegaCore Function User Guide
Notes to
(1) When using the buffered burst architecture, you can specify the number of quad-output FFT engines in the FFT MegaWizard interface.
(2) EP3C10F256C6 device.
(3) EP3C16F484C6 device.
Notes to
(1) When using the buffered burst architecture, you can specify the number of quad-output engines in the FFT MegaWizard interface. You may
(2) In a buffered burst data flow architecture, transform time is defined as the time from when the N-sample input block is loaded until the first
(3) Block throughput is the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.
(4) EP3C10F256C6 device.
(5) EP3C16F484C6 device.
1024
1024
Points
256
256
Points
Points
1024
4096
1024
4096
256
4096
4096
1024
4096
256
256
choose from one, two, or four quad-output engines in parallel.
output sample is ready for output. Transform time does not include the additional N-1 clock cycle to unload the full output data block.
(4)
(5)
(4)
(5)
Table
Table
Quad Output
Quad Output
1–6:
1–7:
Architecture
Engines
Number of
Engines
Number of
Engine
2
4
4
4
1
1
1
2
2
2
4
4
4
Table 1–7
multipliers /2 adders complex multiplier structure, for data and twiddle width 16, for
Cyclone III (EP3C25F324C6) devices.
Table 1–8
/2 adders complex multiplier structure, for data and twiddle width 16, for Cyclone III
(EP3C10F256C6) devices.
(1)
(1)
Combinational
Engines
Number of
lists resource usage with burst data flow architecture, using the 4 multipliers
lists performance with buffered burst data flow architecture, using the 4
fMAX
(MHz)
247
241
227
225
207
215
230
230
215
5337
9015
9145
9241
LUTs
1
1
(2)
Combinational
Transform Calculation
Cycles
1069
5167
1378
Registers
2,07
235
162
557
118
340
10738
10963
11169
3120
3227
LUTs
Logic
6361
Time
(2)
Time (μs)
22.81
12.12
0.95
4.44
0.72
2.69
0.51
1.48
6.4
Registers
Memory
491776
123136
491776
Logic
3694
3876
30976
(Bits)
Data Load & Transform
Cycles
2093
9263
1581
1364
5474
6703
491
397
347
Memory
Calculation
14592
57600
(Bits)
Memory
(M9K)
60
60
60
60
Chapter 1: About This MegaCore Function
Time (μs)
31.17
1.99
8.69
40.9
1.77
7.63
1.51
5.93
25.4
(Part 1 of 2)
© December 2010 Altera Corporation
Memory
Performance and Resource Utilization
(M9K)
8
8
Blocks
9 × 9
48
96
96
96
Cycles
Block Throughput
1291
6157
1163
5133
1099
4633
331
299
283
Blocks
9 × 9
24
24
(3)
Time (μs)
(MHz)
215
230
230
215
f
27.18
23.87
1.34
5.36
1.33
5.61
1.23
4.78
21.5
MAX
(MHz)
232
246
f
MAX