IPR-FFT Altera, IPR-FFT Datasheet - Page 17

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–20. Resource Usage with the Burst Data Flow Architecture—Stratix IV Devices
Table 1–21. Performance with the Burst Data Flow Architecture—Stratix IV Devices (Part 1 of 2)
© December 2010 Altera Corporation
Notes to
(1) Represents data and twiddle factor precision.
(2) When using the burst data flow architecture, you can specify the number of engines in the FFT MegaWizard interface. You may choose from
Points
Points
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
1024
4096
256
256
256
256
256
256
256
256
256
one to two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
Table
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Single Output
Single Output
Single Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Architecture
Architecture
1–20:
Engine
Engine
Table 1–21
/2 adders complex multiplier structure, for data and twiddle width 16, for Stratix IV
(EP4SGX70DF29C2X) devices.
Engines
Number of
Engines
Number of
1
1
1
2
2
2
4
4
4
1
1
1
lists performance with burst data flow architecture, using the 4 multipliers
(1)
1
1
1
2
2
2
4
4
4
1
1
1
2
2
2
(2)
(MHz)
436
446
443
418
412
366
369
385
380
407
413
412
f
MAX
Combinational
ALUTs
1794
1829
1881
2968
3014
3053
5160
5218
5284
1036
1052
1092
704
740
801
Calculation Time
Cycles
24705
1069
5167
2607
1378
1115
5230
235
162
557
118
340
Transform
Registers
Time (μs)
10101
10290
Logic
3502
3684
3852
5489
5680
5856
9891
2332
1436
1482
1528
2408
2484
11.66
12.66
59.91
0.54
2.39
0.39
1.35
7.12
0.32
0.88
3.63
2.74
(2)
Data Load & Transform
Memory
229632
229632
229632
147712
229632
14592
57600
14592
57600
14592
57600
37120
14592
57600
Cycles
28801
(Bits)
9472
2093
9263
1581
6703
1364
5474
1371
6344
491
397
374
Calculation
Time (μs)
Memory
(M9K)
14.42
15.35
69.84
1.12
4.69
20.9
0.95
3.83
18.3
1.01
3.55
3.37
28
15
15
28
28
28
28
19
11
28
8
8
3
6
9
FFT MegaCore Function User Guide
18 × 18
Blocks
Cycles
Block Throughput
32898
1291
6157
1163
5133
1099
4633
1628
7279
331
299
283
12
12
12
24
24
24
48
48
48
4
4
4
8
8
8
(3)
Time (μs)
13.89
14.01
12.20
17.62
79.78
(MHz)
0.76
2.89
0.71
2.82
0.77
2.86
4.00
436
446
443
418
412
366
369
385
380
407
413
412
405
431
406
f
MAX
1–13