IPR-FFT Altera, IPR-FFT Datasheet - Page 36

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–2
Variable Streaming Architecture
FFT MegaCore Function User Guide
f
1
To maintain a high signal-to-noise ratio throughout the transform computation, the
FFT MegaCore function uses a block-floating-point architecture, which is a trade-off
point between fixed-point and full-floating point architectures.
In a fixed-point architecture, the data precision needs to be large enough to
adequately represent all intermediate values throughout the transform computation.
For large FFT transform sizes, an FFT fixed-point implementation that allows for
word growth can make either the data width excessive or can lead to a loss of
precision.
In a floating-point architecture each number is represented as a mantissa with an
individual exponent—while this leads to greatly improved precision, floating-point
operations tend to demand increased device resources.
In a block-floating point architecture, all of the values have an independent mantissa
but share a common exponent in each data block. Data is input to the FFT function as
fixed point complex numbers (even though the exponent is effectively 0, you do not
enter an exponent).
The block-floating point architecture ensures full use of the data width within the FFT
function and throughout the transform. After every pass through a radix-4 FFT, the
data width may grow up to log
measure of the block dynamic range on the output of the previous pass. The number
of shifts is accumulated and then output as an exponent for the entire block. This
shifting ensures that the minimum of least significant bits (LSBs) are discarded prior
to the rounding of the post-multiplication output. In effect, the block-floating point
representation acts as a digital automatic gain control. To yield uniform scaling across
successive output blocks, you must scale the FFT function output by the final
exponent.
In comparing the block-floating point output of the Altera FFT MegaCore function to
the output of a full precision FFT from a tool like MATLAB, the output should be
scaled by 2 (
to
For more information about exponent values, refer to
Point
The variable streaming architecture uses two different types of architecture,
depending on whether you select the fixed-point data representation or the floating
point representation. If you select the fixed-point data representation, the FFT
variation uses a radix 2
architecture. If you select the floating point representation, the FFT variation uses a
mixed radix-4/2 architecture. For a length N transform, log
concatenated together. The radix 2
of a fully pipelined radix-4 architecture, but the butterfly unit retains a radix-2
architecture. In the radix-4/2 algorithm, a combination of radix-4 and radix-2
architectures are implemented to achieve the computational advantage of the radix-4
architecture while supporting FFT computation with a wider range of transform
lengths. The butterfly units use the DIF decomposition.
“Block Floating Point Scaling” on page
Scaling.
–exponent_ou
t
) to account for the discarded LSBs during the transform. (Refer
2
single delay feedback architecture, which is a fully pipelined
2
(4√2) = 2.5 bits. The data is scaled according to a
2
algorithm has the same multiplicative complexity
A–1.)
AN 404: FFT/IFFT Block Floating
© December 2010 Altera Corporation
4
(N) stages are
Chapter 3: Functional Description
Variable Streaming Architecture