PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 97

• Manufacturer Part Number: PIC18C658-I/PT
• Description: 32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658I/PT

8.5
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (=1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISE bit (=0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 8-9).
FIGURE 8-8:
 2000 Microchip Technology Inc.
PORTE, TRISE and LATE Registers
Note 1:
Peripheral Out Select
Peripheral Data Out
Peripheral Data In
Peripheral Enable
RD PORTE
WR TRISE
WR LATE
or
WR PORTE
Data Bus
PORTE BLOCK DIAGRAM
I/O pins have diode protection to V
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Pin
TRIS Latch
Data
D
D
CK
RD TRISE
CK
Latch
RD LATE
Override
Q
Q
Q
Q
Advanced Information
Yes
Yes
Yes
No
No
No
No
No
TRIS OVERRIDE
DD
Peripheral
PSP
PSP
PSP
—
—
—
—
—
and V
Override
TRIS
SS
0
1
.
Q
EXAMPLE 8-5:
CLRF
CLRF
MOVLW
MOVWF
EN
D
PORTE
LATE
0x03
TRISE
Schmitt
Trigger
V
V
N
P
SS
DD
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
PIC18CXX8
DS30475A-page 97
I/O Pin
(1)