PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 241

• Manufacturer Part Number: PIC18C658-I/PT
• Description: 32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658I/PT

19.6
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the comparator interrupt flag. The
CMIF bit must be RESET by clearing ‘0’. Since it is also
possible to write a '1' to this register, a simulated inter-
rupt may be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
.
Note:
2000 Microchip Technology Inc.
Any read or write of CMCON will end the mis-
match condition.
Clear flag bit CMIF.
Comparator Interrupts
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR regis-
ters) interrupt flag may not get set.
Advanced Information
19.7
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode, when enabled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parator specifications. To minimize power consumption
while in SLEEP mode, turn off the comparators,
CM<2:0> = 111, before entering SLEEP. If the device
wakes up from SLEEP, the contents of the CMCON
register are not affected.
19.8
A device RESET forces the CMCON register to its
RESET state, causing the comparator module to be in
the comparator RESET mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered down during the RESET interval.
Comparator Operation During SLEEP
Effects of a RESET
PIC18CXX8
DS30475A-page 241