PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 258

• Manufacturer Part Number: PIC18C658-I/PT
• Description: 32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658I/PT

PIC18CXX8
22.3.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
• If the interrupt condition occurs during or after
FIGURE 22-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT
DS30475A-page 258
Note 1:
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
the execution of a SLEEP instruction, the device
will immediately wake-up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
INSTRUCTION FLOW
Instruction
fetched
CLKOUT
Instruction
executed
2:
3:
4:
INTIF bit
GIEH bit
INT pin
OSC1
WAKE-UP USING INTERRUPTS
PC
(4)
XT, HS or LP oscillator mode assumed.
GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE is cleared, execution will continue in-line.
T
CLKOUT is not available in these oscillator modes, but shown here for timing reference.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
(drawing not to scale). This delay will not occur for RC and EC osc modes.
Q1 Q2 Q3 Q4
Inst(PC + 2)
SLEEP
PC+2
Q1
Processor in
Advanced Information
SLEEP
PC+4
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 4)
Inst(PC + 2)
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
PC+4
Interrupt Latency
Dummy cycle
(1,2)
PC + 4
(3)
Q1 Q2 Q3 Q4
2000 Microchip Technology Inc.
Inst(0008h)
Dummy cycle
0008h
Q1 Q2 Q3 Q4
Inst(000Ah)
Inst(0008h)
000Ah