PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 284

• Manufacturer Part Number: PIC18C658-I/PT
• Description: 32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658I/PT

PIC18CXX8
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS30475A-page 284
Before Instruction
After Instruction
Decode
WREG
N
Z
WREG
N
Z
Q1
=
=
=
=
=
=
Inclusive OR literal with WREG
[ label ]
0
(WREG) .OR. k
N,Z
The contents of WREG are OR’ed
with the eight bit literal 'k'. The
result is placed in WREG.
1
1
literal ’k’
IORLW
Read
0000
Q2
0x9A
?
?
0xBF
1
0
k
255
IORLW k
1001
0x35
Process
Data
Q3
WREG
kkkk
Advanced Information
Write to W
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
RESULT =
WREG
N
Z
RESULT =
WREG
N
Z
Q1
=
=
=
=
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
a
(WREG) .OR. (f)
N,Z
Inclusive OR W with register 'f'. If 'd'
is 0, the result is placed in WREG.
If 'd' is 1, the result is placed back
in register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1
IORWF
Read
0001
Q2
0x13
0x91
?
?
0x13
0x93
1
0
f
[0,1]
[0,1]
2000 Microchip Technology Inc.
255
RESULT, W
IORWF
00da
Process
Data
Q3
ffff
f [ ,d [,a] ]
dest
destination
Write to
Q4
ffff