PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 88
![32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C658-I/PT
Manufacturer Part Number
PIC18C658-I/PT
Description
32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C658I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-I/PT
Manufacturer:
Microchip
Quantity:
601
Company:
Part Number:
PIC18C658-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 88 of 366
- Download datasheet (7Mb)
PIC18CXX8
7.1.6
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2, and RB3/INT3 pins are edge triggered:
either rising if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit INTxIF is set. This interrupt
can be disabled by clearing the corresponding enable
bit INTxIE. Flag bit INTxIF must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2, and
INT3) can wake-up the processor from SLEEP, if bit
INTxIE was set prior to going into SLEEP. If the global
interrupt enable bit GIE is set, the processor will branch
to the interrupt vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits
INT1IP (INTCON3 register), INT3IP (INTCON3 regis-
ter), and INT2IP (INTCON2 register). There is no prior-
ity bit associated with INT0; it is always a high priority
interrupt source.
7.1.7
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
EXAMPLE 7-1:
DS30475A-page 88
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INT INTERRUPTS
TMR0 INTERRUPT
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
Advanced Information
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit TMR0IE (INTCON register). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 10.0 for further details on the Timer0 module.
7.1.8
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-
on-change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
7.2
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR reg-
isters are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved.
Example 7-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
PORTB INTERRUPT-ON-CHANGE
Context Saving During Interrupts
2000 Microchip Technology Inc.
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