PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 60

32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY

PIC18C658-I/PT

Manufacturer Part Number
PIC18C658-I/PT
Description
32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Cr

Specifications of PIC18C658-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
PIC18C658I/PT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18C658-I/PT
Manufacturer:
Microchip
Quantity:
601
Part Number:
PIC18C658-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18CXX8
4.10
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also be useful
for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFR’s (no banking)
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFR’s) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-4
indicates the Access Bank areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register, or in
the Access Bank.
When forced in the Access Bank (a = ’0’), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
most of the Special Function Registers so that these
registers can be accessed without any software over-
head.
FIGURE 4-5:
DS30475A-page 60
Note 1: For register file map detail, see Table 4-2.
Access Bank
bank select
2: The access bit of the instruction can be used to force an override of the selected bank
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
(BSR<3:0>) to the registers of the Access Bank.
DIRECT ADDRESSING
BSR<3:0>
(2)
location select
7
Direct Addressing
Data
Memory
from opcode
Advanced Information
(1)
(3)
(3)
000h
0FFh
Bank 0
00h
4.11
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A MOVLB instruction has been provided in the instruc-
tion set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
0
100h
1FFh
Bank 1
01h
Bank Select Register (BSR)
 2000 Microchip Technology Inc.
E00h
EFFh
Bank 14
0Eh
F00h
FFFh
Bank 15
0Fh

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