PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 222

• Manufacturer Part Number: PIC18C658-I/PT
• Description: 32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658I/PT

PIC18CXX8
17.9
Some requirements for programming of the time
segments:
• Prop Seg + Phase Seg 1
• Phase Seg 2
For example, assuming that a 125 kHz CAN baud rate
with F
T
T
16 T
Sync Seg = 1 T
Seg 1 = 7 T
transition. This would leave 6 T
Since Phase Seg 2 is 6, by the rules, SJW could be the
maximum of 4 T
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. So an SJW of 1 is typically
enough.
17.10
The bit timing requirements allow ceramic resonators
to be used in applications with transmission rates of up
to 125 kbit/sec, as a rule of thumb. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
DS30475A-page 222
OSC
Q
= 500nsec. To obtain 125 kHz, the bit time must be
Q
.
OSC
= 50nsec, choose BRP<5:0> = 04h, then
Programming Time Segments
Oscillator Tolerance
= 20 MHz is desired:
Q
would place the sample at 10 T
Q
Q
; Prop Seg = 2 T
Sync Jump Width
. However, normally a large SJW is
Phase Seg 2
Q
for Phase Seg 2.
Q
; So, setting Phase
Advanced Information
Q
after the
17.11
The configuration registers (BRGCON1, BRGCON2,
BRGCON3) control the bit timing for the CAN bus inter-
face. These registers can only be modified when the
PIC18CXX8 is in Configuration mode.
17.11.1 BRGCON1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of number of T
17.11.2 BRGCON2
The PRSEG bits set the length, in T
tion segment. The SEG1PH bits set the length, in T
of phase segment 1. The SAM bit controls how many
times the RXCAN pin is sampled. Setting this bit to a ‘1’
causes the bus to be sampled three times; twice at
T
sample point (which is at the end of phase segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of phase segment 2 is determined. If this bit is
set to a ‘1’, then the length of phase segment 2 is deter-
mined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of phase
segment 2 is the greater of phase segment 1 and the
information processing time (which is fixed at 2 T
the PIC18CXX8).
17.11.3 BRGCON3
The PHSEG2<2:0> bits set the length, in T
phase segment 2, if the SEG2PHTS bit is set to a ‘1’. If
the SEG2PHTS bit is set to a ‘0’, then the
PHSEG2<2:0> bits have no effect.
Q
/2 before the sample point, and once at the normal
Bit Timing Configuration Registers
Q
’s.
2000 Microchip Technology Inc.
Q
’s, of the propaga-
Q
’s, of
Q
Q
for
’s,