PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 161

• Manufacturer Part Number: PIC18C658-I/PT
• Description: 32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658I/PT

15.4.12 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 15-19).
FIGURE 15-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
 2000 Microchip Technology Inc.
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval.
SCL
SDA
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
Advanced Information
T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
15.4.13 SLEEP OPERATION
While in SLEEP mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
15.4.14 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
T
SCL = 1 BRG starts counting
clock high interval.
BRG
PIC18CXX8
2
C module can receive
OSC
DS30475A-page 161
² 4).