AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 67

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-72 •
Table 2-73 •
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at
2. For specific junction temperature and voltage supply levels, refer to
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. For specific junction temperature and voltage supply levels, refer to
3. Software default selection highlighted in gray.
the equivalent software default drive strength. These values are for normal ranges only.
equivalent software default drive strength. These values are for normal ranges only.
Equivalent
Software
Equivalent
Strength
Option
Commercial-Case Conditions: T
Applicable to Advanced Banks
Commercial-Case Conditions: T
Applicable to Advanced Banks
Default
Software
Strength
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
12 mA
16 mA
24 mA
Option
Drive
Default
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Drive
4 mA
6 mA
8 mA
Applies to 1.2 V DC Core Voltage
1
1
Speed
Grade t
Speed
Grade
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
DOUT
1.55
1.55
1.55
1.55
1.55
1.55
t
DOUT
1.55
1.55
1.55
1.55
1.55
1.55
7.52 0.26 1.32
6.37 0.26 1.32
6.37 0.26 1.32
5.55 0.26 1.32
5.32 0.26 1.32
5.19 0.26 1.32
t
DP
4.75 0.26 1.32
4.10 0.26 1.32
4.10 0.26 1.32
3.73 0.26 1.32
3.67 0.26 1.32
3.70 0.26 1.32
t
DP
J
J
t
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7
DIN
t
DIN
t
PY
R ev i si o n 1 8
t
PY
t
1.10
1.10
1.10
1.10
1.10
1.10
EOUT
t
EOUT
1.10
1.10
1.10
1.10
1.10
1.10
Table 2-6 on page 2-7
Table 2-6 on page 2-7
7.52 6.38 3.84 4.02 13.31 12.16
6.37 5.57 4.23 4.73 12.16 11.35
6.37 5.57 4.23 4.73 12.16 11.35
5.55 4.96 4.50 5.18 11.34 10.75
5.32 4.82 4.56 5.29 11.10 10.61
5.19 4.85 4.63 5.74 10.98 10.63
t
ZL
4.75 3.77 3.84 4.27 10.54 9.56
4.10 3.19 4.24 4.98
4.10 3.19 4.24 4.98
3.73 2.91 4.51 5.43
3.67 2.85 4.57 5.55
3.70 2.79 4.65 6.01
t
ZL
t
ZH
t
ZH
t
LZ
t
LZ
IGLOO Low Power Flash FPGAs
for derating values.
for derating values.
t
HZ
t
HZ
t
ZLS
9.88
9.88
9.52
9.46
9.49
t
ZLS
t
ZHS
t
8.98
8.98
8.69
8.64
8.58
ZHS
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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