AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 55

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-46 • Minimum and Maximum DC Input and Output Levels
Table 2-47 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
3.3 V LVTTL /
3.3 V LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges.
larger when operating outside recommended ranges
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V
software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification.
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
V
VIL
VIL
Max.
Max.
0.8
0.8
0.8
0.8
0.8
0.8
V
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
Min.
Min.
V
2
2
2
2
2
2
V
2
2
2
2
2
2
2
VIH
VIH
Max.
Max.
3.6
3.6
3.6
3.6
3.6
3.6
V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
Max.
V
Max.
0.4
0.4
0.4
0.4
0.4
0.4
VOL
V
OL
0.4
0.4
0.4
0.4
0.4
0.4
0.4
R ev i si o n 1 8
V
VOH
Min.
2.4
2.4
2.4
2.4
2.4
2.4
VOH
V
Min.
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V
mA mA
I
OL
12
16
mA mA
2
4
6
I
8
24 24
OL
12 12
16 16
2
6
4
8
I
I
OH
12
16
2
6
OH
4
8
2
6
4
8
Max.
mA
Max.
I
mA
103
103
I
103
OSL
132
268
25
25
51
51
OSL
25
25
51
51
3
IGLOO Low Power Flash FPGAs
3
Max.
I
mA
Max.
109
109
OSH
I
mA
109
27
27
54
54
127
181
OSH
27
27
54
54
3
3
µA
I
µA
10
10
I
IL
10
10
10
10
IL
10
10
10
10
10
10
10
1
4
1
4
µA
µA
I
I
10
10
IH
2- 41
10
10
10
10
IH
10
10
10
10
10
10
10
2
2
4
4