AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 109

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-22 • Input DDR Timing Diagram
Table 2-163 • Input DDR Propagation Delays
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
Commercial-Case Conditions: T
1.5 V DC Core Voltage
t
t
1
DDRICLR2Q1
DDRICLR2Q2
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (negedge)
Data Setup for Input DDR (posedge)
Data Hold for Input DDR (negedge)
Data Hold for Input DDR (posedge)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
t
DDRIREMCLR
2
3
t
DDRICLKQ1
J
= 70°C, Worst-Case VCC = 1.425 V
4
Description
2
R ev i si o n 1 8
3
5
t
DDRICLKQ2
t
DDRISUD
Table 2-7 on page 2-7
6
4
5
7
IGLOO Low Power Flash FPGAs
t
DDRIHD
t
for derating values.
8
DDRIRECCLR
6
7
TBD
0.48
0.65
0.50
0.40
0.00
0.00
0.82
0.98
0.00
0.23
0.19
0.31
0.28
Std.
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 95