AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 231

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 4 (Mar 2008)
Product Brief v1.0
Revision 3 (Feb 2008)
Product Brief rev. 2
Packaging v1.2
Revision 2 (Jan 2008)
Packaging v1.1
Revision 1 (Jan 2008)
Product Brief rev. 1
Revision 0 (Jan 2008)
Advance v0.7
(December 2007)
The
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed
from "Low Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the
"I/Os with Advanced I/O Standards" section
The
from the section heading and place it instead after "4,608-Bit" and "True Dual-
Port SRAM (except ×18)."
This document was updated to include AGL015 device information. QN68 is a
new package offered in the AGL015. The following sections were updated:
"Features and Benefits"
"IGLOO Ordering Information"
"Temperature Grade Offerings"
"IGLOO Devices"
Table 1 • IGLOO FPGAs Package Sizes Dimensions
"AGL015 and AGL030"
The
In the
updated to include both 0.4 mm and 0.5 mm.
In the
300.
The
The
The
active FPGA operation to "from 12 µW" from "from 25 µW." The same update
was made in the
Technology"
This document was previously in datasheet Advance v0.7. As a result of moving
to the handbook format, Actel has restarted the numbering.
Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the
Temperature Grade Offerings table were updated to reflect the following: CS196
is now supported for AGL250; device/package support for QN132 is to be
determined for AGL250; the CS281 package was added for AGL600 and
AGL1000.
Table 2 • IGLOO FPGAs Package Sizes Dimensions is new, and package sizes
were removed from the "I/Os Per Package1" table.
The "I/Os Per Package1"table was updated to reflect 77 instead of 79 single-
ended I/Os for the VG100 package for AGL030.
The
numbers.
In
Applicable to Commercial and Industrial Conditions—Software Default
T
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
J
Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels
was changed to T
"Low Power" section
"Embedded Memory" section
"Temperature Grade Offerings"
"68-Pin QFN"
"196-Pin CSP"
"Low Power" section
"Timing Model"
"IGLOO Ordering Information"
"General Description"
section.
Product Family Table
section is new.
package and pin table was added for AGL125.
A
"General Description" section
was updated to be consistent with the revised timing
in notes 1 and 2.
note
was updated to change "1.2 V and 1.5 V Core Voltage"
was updated to change the description of low power
section, the number of I/Os was updated from 288 to
R ev i si o n 1 8
was updated to remove the footnote reference
Changes
table was updated to include M1AGL600.
table, the QN package measurements were
sections.
and the
"Advanced I/O"
IGLOO Low Power Flash FPGAs
"Flash*Freeze
Settings,
and
i, ii, iv
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2-20
2-26
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N/A
N/A
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III
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