AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 141

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-193 • RAM512X18
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
DS
DH
CKQ1
CKQ2
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same address -
Applicable to Opening Edge
Address collision clk-to-clk delay for reliable write access after read on same address -
Applicable to Opening Edge
RESET_B Low to data out Low on DO (flow through)
RESET_B Low to data out Low on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i si o n 1 8
Table 2-7 on page 2-7
IGLOO Low Power Flash FPGAs
for derating values.
10.90
1.53
0.29
1.36
1.33
0.87
1.04
3.86
3.86
1.12
5.93
1.18
Std.
0.15
0.66
7.88
3.20
92
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 127