AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 43

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
3.3 V
LVTTL /
3.3 V
LVCMOS
3.3 V
LVCMOS
Wide
Range
2.5 V
LVCMOS
1.8 V
LVCMOS
1.5 V
LVCMOS
3.3 V PCI
3.3 V
PCI-X
LVDS
LVPECL
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
4. For specific junction temperature and voltage supply levels, refer to
equivalent software default drive strength. These values are for normal ranges only.
connectivity. This resistor is not required during normal operation.
2
Per PCI
100 µA
12 mA
12 mA
12 mA
12 mA
PCI-X
24 mA
24 mA
spec
spec
Commercial-Case Conditions: T
standard)
Applicable to Advanced I/O Banks
Per
12
12
12
12
12
–
–
–
–
High
High
High
High
High
High
High
High
High
10
10
5
5
5
5
5
–
–
25
25
–
–
–
–
–
–
–
2
2
J
0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27 ns
0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87 ns
0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43 ns
0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns
0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns
0.97 2.32 0.18 0.74 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns
0.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns
0.97 1.74 0.19 1.35
0.97 1.68 0.19 1.16
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
R ev i si o n 1 8
μ
A drive strength only. The configuration will not operate at the
Table 2-6 on page 2-7
–
–
–
–
–
–
IGLOO Low Power Flash FPGAs
for derating values.
Figure 2-12 on page 2-79
–
–
–
–
–
–
–
–
2- 29
ns
ns
for